HT82V46 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
Manufacturer
HT82V46 Datasheet PDF : 27 Pages
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HT82V46
Analog
Input
(R, G)
CDS1
Pixel n
Pixel n+1
t ADFC1R
t C1
t C1FC2R
Pixel n+2
t PR2
t C2
Pixel n+3
CDS2
t ADFC2R
tC2FADR
ADCK
t ADH
t ADL
t OD
OD[7:0]
G
G
HB
LB
R
R
G
G
R
R
HB
LB
HB
LB
HB
LB
G
G
R
R
G
HB
LB
HB
LB
HB
n-5
n-4
n-3
n-2
HB : High Byte; LB : Low Byte
Figure 3 2-channel CDS Analog Input Timing
tOD
G
R
LB
HB
n-1
Analog
Input
(R)
CDS1
Pixel n
t ADFC1R
t C1FC2R
Pixel n+1
t C1
t C2
Pixel n+2
t PR1
ADFC2R
Pixel n+3
CDS2
t C2FADR
t ADFC2F
ADCK
t ADH
t ADL
t ADC
t OD
OD[7:0]
R
R
HB
LB
R
R
HB
LB
R
R
HB
LB
n-8
n-7
n-6
HB : High Byte; LB : Low Byte
Figure 4 1-channel CDS Analog Input Timing
t OD
R
R
HB
LB
n-5
Note: 1. The relationship between input video and sampling is controlled by CDS2 and CDS1.
2. When CDS2 is high the input video signal is connected to the Video level sampling capacitors.
3. When CDS1 is high the analog input video signal is connected to the Reference level sampling capacitors.
4. CDS1 must not go high before the first falling edge of ADCK after CDS2 goes low.
5. It is required that the falling edge of CDS2 should occur before the rising edge of ADCK.
6. In 1-channel CDS mode it is not possible to have a equally spaced Video and Reference sample points
with a 45MHz ADCK.
7. Non-CDS operation is also possible; CDS1 is not required in this mode.
Rev. 1.10
9
November 24, 2011
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