HT82V842 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
Manufacturer
HT82V842 Datasheet PDF : 18 Pages
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B la n k in g
CCD
E ffe c tiv e P ix e l
S ig n a l
O p tic a l B la c k P e r io d
B la n k in g
HT82V842
E ffe c tiv e P ix e l
S ig n a l
ADCK
O BP
O BCAP
P r e v io u s B la c k
Level
Black Level Calibration Timing
R e s u ltin g B la c k
C a lib r a tio n L e v e l
( H o ld )
High-speed Black Level Cancellation
The HT82V842 has a high speed black level cancella-
tion function, which by means of a register setting en-
hances the settling speed within a fixed period from
access to the serial interface. It increases the gain of the
setting DAC within a fixed period and in turn increases
the charge/discharge current to the OBCAP capacitor.
The Mode 3 register D3 to D0 data controls the black
level boost function. The default setting is always low
gain (D3~D0=5¢b0). By setting the register D2~D0, the
gain becomes high by 1 to 7 times that of the OBP pulse
period after any access to the serial interface. After that
period, the gain returns to low. When setting D3 to 1¢b1,
the gain is always high. The CS signal becomes the
starting point of the OBP pulse count.
The following figure shows the black loop settling gain
boost timing chart when the boost control is on (D3=²0²)
and the boost period is set to 3.
CS
tS U C S
tH C S
O BP
C o u n te r
0
1
2
3
3
0
B la c k lo o p
g a in
H ig h g a in
L o w g a in
Symbol
Parameter
tSUCS
CS Setup Time
tHCS
CS Hold Time
Black Loop Settling Gain Boost Timing
Condition
Min.
Typ.
¾
10
¾
¾
10
¾
1
2
0
H ig h g a in
1
2
Max.
Unit
¾
ns
¾
ns
Gain Control Circuit
The total gain for a CCD input signal covers from
-1.94dB to 36dB. The CDS range is 0/6/12/-1.94 dB.
The PGA rough is 0/6/12/18dB and ADC fine is 0 to
6dB, 0.047dB/step. The CDS gain is controlled by a
2-bit register and the PGA gain is controlled by a 9-bit
register.
A/D Converter Circuit
The HT82V842 includes one 20MHz 10 bits AD con-
verter. The ADC converts the following signals.
· The signal from the CCDIN input through a CDS and
PGA.
· The signal from the ADIN input through an PGA at the
ADIN mode.
· The signal from the ADIN input at the ADIN mode.
A/D Conversion Range
The analog input range of the ADC is determined by the
internal reference voltage. The full scale of the ADC is
1.0 VPP.
Rev. 1.00
6
July 15, 2004
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