HV9608TS View Datasheet(PDF) - Supertex Inc
Part Name
Description
Manufacturer
HV9608TS Datasheet PDF : 6 Pages
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HV9608
Electrical Characteristics (continued from page 3) (The * denotes the specifications which apply over the full
operating temperature range of -40°C < TA < +85°C, otherwise the specifications are at TA = 25°C, VDD = 10V, unless otherwise noted)
Slope Compensation
Symbol
Parameter
Min
RSC
Slope compensation resistor range 5
IRAMP,PEAK
Slope compensation ramp peak
current
125
Max Duty-Cycle/Voltage-Second Clamp
Symbol
Parameter
Iin
VS pin input current range
DVS
Duty cycle of gate signal
DVS
Duty cycle of gate signal
DVS
Duty cycle of gate signal
Min
50µ
50
23
21.5
Typ
150
Typ
55.5
25.5
25.5
Max Units
kΩ
175 µA
Conditions
RT = 453KΩ; RCS = 500Ω;
RSC = 40KΩ; Full duty cycle
Max
3m
61
28
29
Units
A
%
%
%
Conditions
Ivs = 250µA, RDT1 = RDT2 = 80K;
RT = 169K
Ivs = 510µA, RDT1 = RDT2 = 80K;
RT=169K
*
Ivs = 510µA, RDT1 = RDT2 = 80K;
RT=169K
Pinout
VIN 1
UVLO 2
REF 3
SS 4
SC 5
RT 6
VS 7
COMP 8
HV9608
16 VDD
15 DT1
14 AGATE
13 GATE
12 DT2
11 GND
10
CS
9
FB
Pin Descriptions
VIN – This is the high voltage linear regulator input. It can accept
DC input voltages in the range of 12V to 250V, and supplies a
regulated voltage of 9.5V to the VDD pin.
UVLO – This pin can be used for enabling/disabling the HV9608,
or as an under voltage lockout input. Both the turn-on and the
turn-off thresholds are independently programmable. By selecting
appropriate resistor values, a corresponding voltage divider is
connected to this pin. When the voltage on this pin falls below a
threshold, the high voltage regulator turns-off and the HV9608
becomes disabled.
VDD – This is the power supply pin for the PWM logic and analog
circuits. When the input voltage to the VIN pin exceeds the start
voltage of 8.5V, the input regulator will bias the voltage at this pin
to a nominal of 9.5V. After the PWM has started, an external
bootstrap supply can overdrive the output voltage of the regulator
disconnecting it from VIN. Bypass this pin to GND using a low
impedance high frequency capacitor.
REF – This pin provides a 2% accurate reference voltage that can
source up to 2mA of current.
SS – A capacitor connected to this pin determines the soft start
time. The soft start capacitor is fully discharged upon detection of
the under voltage condition at VDD or UVLO pins.
VS – The resistor connected from this pin to VIN sets the charging
current to an internal capacitor, which is matched with the
oscillator capacitor. The voltage on the capacitor is compared with
a reference voltage of 1.2V, and sets the maximum duty ratio of
the PWM controller.
SC – The resistor connected from this pin to GND sets the ramp
current sourced from the CS pin for slope compensation.
RT – The resistor connected from this pin to GND programs the
frequency of the internal oscillator by setting the charging current
for the internal timing capacitor.
GND – Common connection for all Logic and Analog circuits.
AGATE – This push-pull CMOS output is designed to drive the
gate of an external P-Channel power MOSFET.
GATE – This push-pull CMOS output is designed to drive the gate
of an external N-Channel power MOSFET.
DT2 – This pin is used to set the dead time between the falling
edge of GATE signal and AGATE signal.
DT1 – This pin is used to set the dead time between the rising
edge of AGATE signal and GATE signal.
FB – High impedance inverting input of the error amplifier.
COMP – The output of the error amplifier.
CS – A resistor connected from this pin to a current sense voltage
programs the amount of slope compensation ramp and feeds this
current sense voltage to the PWM comparator. A leading edge
blanking of 100ns is provided. Voltage of 0.6V at this pin triggers
the current limit comparator.
4
A122104
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