HYB39S64800BTL-8 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

HYB39S64800BTL-8

64-MBit Synchronous DRAM

Infineon Technologies 

HYB 39S64400/800/160BT(L)

64-MBit Synchronous DRAM

Notes

1. For proper power-up see the operation section of this data sheet.

2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover

point. The transition time is measured between VIH and VIL. All AC measurements assume

tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters

are measured with a 50 pF only, without any resistive termination and with a input signal of 1V /

ns edge rate between 0.8 V and 2.0 V.

CLOCK

t CL

t SETUP

t HOLD

INPUT

OUTPUT

1.4 V

tAC

t LZ

t CH

2.4 V

0.4 V

tT

tAC

t OH

1.4 V

t HZ

SPT03404

I/O

50 pF

Measurement conditions for

tAC and tOH

3. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns has to be added to this parameter.

4. If tT is longer than 1 ns, a time (tT − 1) ns has to be added to this parameter.

5. These parameter account for the number of clock cycle and depend on the operating frequency

of the clock, as follows:

the number of clock cycle = specified value of timing period (counted in fractions as a whole

number)

6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after

CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied

once the Self Refresh Exit command is registered.

Data Book

19

12.99

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