HYB39S64800BT-8 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

HYB39S64800BT-8

64-MBit Synchronous DRAM

Infineon Technologies 

HYB 39S64400/800/160BT(L)

64-MBit Synchronous DRAM

Signal Pin Description (cont’d)

Pin

Type Signal Polarity Function

DQM

LDQM

UDQM

Input Pulse Active

High

The Data Input/Output mask places the DQ buffers in a

high impedance state when sampled high. In Read mode,

DQM has a latency of two clock cycles and controls the

output buffers like an output enable. In Write mode, DQM

has a latency of zero and operates as a word mask by

allowing input data to be written if it is low but blocks the

write operation if DQM is high.

One DQM input it present in ×4 and ×8 SDRAMs, LDQM

and UDQM controls the lower and upper bytes in ×16

SDRAMs.

VDD

VSS

VDDQ

VSSQ

VREF

Supply –

–

Supply –

–

Input Level –

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to

provide improved noise immunity.

Reference voltage for SDRAM versions supporting SSTL

interface

Data Book

8

12.99

Share Link: