ICL7121 View Datasheet(PDF) - Intersil
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ICL7121 Datasheet PDF : 10 Pages
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ICL7121
TABLE 1. 2’S COMPLEMENT BIPOLAR OPERATION
DIGITAL INPUT
MSB
LSB
ANALOG OUTPUT
0000
1111
1000
1000
1000
0000
1111
0000
0000
0000
0000
1111
0000
0000
0000
0000
1111
0010
0001
0000
0
+VREF (1/215)
+VREF (1 - 1/214)
+VREF (1 - 1/215)
+VREF
Amplifier A1 is the output amplifier. An additional amplifier
A2 may be used to force AGNDF if the ground reference
piont is established elsewhere that at the DAC, as in Figure
2.
VOS op amp.
Digital Interface
The ICL7121 has a 16-bit latch onboard and can interface
directly to a 16-bit data bus. As shown in Figure 4, external
latches or peripheral ICs can be used to interface to an 8-bit
data bus. To ensure that the data is written into the onboard
latch, the data must be valid 200ns before the rising edge of
WR. If WR and CS are both low, the onboard latch is
transparent and the input data is directly applied to the
internal R-2R ladder switches. While this simplifies
interfacing in non-microprocessor systems, having WR low
before data is valid may cause additional glitchews in some
microprocessor systems. To avoid these glitches, data must
be valid at the time WR goes low.
A feedback compensation capacitor, CF, improves the
settling time by reducing ringing. This capacitor is normally in
the 10pF - 40pF range, depending on layout and the output
amplifier selected. If CF is too small, rigning or oscillation
can occur when using an op amp with a high gain
bandwidth. If CF is too large, the response of the output
amplifier will be overdamped and will settle slowly.
The input circuits of some high speed op amps will sink large
currents to their negative supply during power up and power
down. The Schottky diode at IOUT limits any negative-going
transitions to less than -0.4V, avoiding the SCR latchup
which could result if significant current was injected into the
parasitic diode between IOUT and DGND of the ICL7121.
This diode is not needed when using the ICL7650 ultra low
All digital interfaces can suffer from capacitive coupling
between the digital lines and the analog section. There are
two general precautions that will reduce this capacitive
coupling problem: 1) reduce stray capacitance between
digital lines and analog lines; and 2) reduce the number of
transitions on the digital inputs. Careful board layout and
shielding can minimize the capacitive coupling (see Figure
5). The activity on the digital input lines can be reduced by
using external latches or peripheral interface ICs between
the microprocessor bus and the ICL7121. This will reduce
the number of transitions on the digital data and control lines
of the ICL7121, thereby reducing the amount of digital noise
coupled into the sensitve analog sections.
FIGURE 4. INTERFACE TO 8-BIT MICROPROCESSOR
8
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