AV1890Y-14 View Datasheet(PDF) - Integrated Circuit Systems

Part Name

Description

Manufacturer

AV1890Y-14

10Base-T/100Base-TX Integrated PHYceiver™

Integrated Circuit Systems 

ICS1890

Introduction

The ICS1890 is essentially a nibble/bit stream processor.

When transmitting, it takes sequential nibbles presented at

the Media Independent Interface (MII) and translates them to

a serial bit stream for transmission on the media. When receiving,

it takes the serial bit stream from the media and translates it to

sequential nibbles for presentation to the MII. It has no

knowledge of the underlying structure of the MAC frame it is

conveying.

100Base-TX Operation

When transmitting, the ICS1890 encapsulates the MAC

frame (including the preamble) with the start-of-stream and

end-of-stream delimiters. When receiving, it strips off the

SSD and substitutes the normal preamble pattern and then

presents this and subsequent preamble nibbles to the MII.

When it encounters the ESD, it ends the presentation of

nibbles to the MII. Thus, the MAC reconciliation layer sees

an exact copy of the transmitted frame.

During periods when no frames are being transmitted or

received, the device signals and detects the idle condition.

This allows the higher levels to determine the integrity of the

connection. In the 100Base-TX mode, a continuous stream of

scrambled ones is transmitted signifying the idle condition.

The receive channel includes logic that monitors the IDLE

data stream to look for this pattern and thereby establishes

the link integrity.

The 100M Stream Interface option allows access to raw groups

of 5-bit data with lower latency through the PHY. This is useful

in building repeaters where latency is critical.

10Base-T Operation

In 10Base-T mode, the bit stream on the cable is identical to

the de-composed MAC frame. Link pulses are used to establish

the channel integrity. When receiving, the ICS1890 first

synchronizes to the preamble. Once lock is detected, it begins

to present preamble nibbles to the MII. On detection of the

SFD, it frames the subsequent 4-bits which are the first data

nibble.

Configuration

The ICS1890 is designed to be fully configurable using

either hardware pins or the (usually) software-driven MII

Management interface, as selected with the HW/SW pin. A

rich set of configuration options are provided. This allows

diverse system implementations and costs.

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