AV1890Y-14 View Datasheet(PDF) - Integrated Circuit Systems

Part Name

Description

Manufacturer

AV1890Y-14

10Base-T/100Base-TX Integrated PHYceiver™

Integrated Circuit Systems 

ICS1890

MII Management Interface

The MII also specifies a two-wire management interface and a

protocol between station management and the physical layer.

The ICS1890 implements this interface, providing a

bidirectional data line and a clock input for synchronizing the

data transfers. This interface allows station management to

read from and write to all of the device’s registers.

Twisted Pair Interface

TheICS1890is able to operate in either 10Base-T or 100Base-

TX modes using a shared interface to a universal magnetics

module and single RJ-45 connector jack.

The interface signals consist of a differential pair of transmit

signals and a differential pair of receive signals. The interface

also provides pins for setting the 10 & 100M transmit current.

It is imperative that the crystal be cut for accuracy and

temperature coeffieients with the equivalent capacitive loading

of the specific board layout and the chosen neutralizing

capacitors. The overall accuracy for ethernet applications

must be ±50ppm total for accuracy, temperature, and aging.

Therefore the crystal must be cut using a fixture with the

equivalent capacitive loading as in the end application. This

custom “cutting” of the crystal will be at additional cost, but

in high volume applications this may be cost effective compared

to “pretuned” crystal oscillator modules. For more information,

contact ICS Datacom Applications.

Configuration and Status Interface

This interface provides a full set of pins to allow the device

to be completely configured by hardware.

Clock Reference Interface

The ICS1890 synthesizes all its required clock signals from

a single 25MHz frequency reference supplied to the Clock

Reference Interface (REF_IN & REF_OUT).

Any reference must meet the stringent IEEE standard

requirements for total accuracy under all conditions of ±50

parts per million (ppm), even though the device can easily

function with a less accurate reference.

Three reference configurations are supported.

The interface also provides dynamic tristate control over

both the Twisted Pair Transmit interface and the MII Receive

interface.

Link Status and Stream Cipher Locking status signals are

provided for use by a MAC or custom logic.

PHY Address & LED Interface

The ICS1890 device uses a unique scheme to multiplex the

PHY Address and the LED outputs onto the same set of five

pins.

A simple CMOS level signal may be fed into the REF_IN

input, leaving the REF-output unconnected.

A crystal oscillator module may be used to provide the

frequency reference for the REF_IN input instead of simple

reference.

Simply connecting the LED from the device pin to either

power or ground sets the address bit to a 1 or 0. The device

then uses the address info to drive the LED correctly

independent of its connection. The Pin Description section

provides detailed connection instructions.

It is possible to use a high precision crystal between the

REF_IN and REF_OUT pins on the ICS1890 to provide the

25MHz time base for part operation. In addition to the

connection of the crystal between these pins, a capacitor

from REF_IN and REF_OUT to ground is necessary to

neutralize the capacitance of the crystal. Since these capacitors

are nominally in series, the values of each of these components

(plus stray board capacitance) will equal twice the rated

capacitance of the crystal (series combination).

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