ICS650-07B View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
Manufacturer
ICS650-07B Datasheet PDF : 4 Pages
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ICS650-07B
Broadcom Clock Source
Description
Features
The ICS650-07B is a low cost, low jitter, high
performance clock synthesizer customized for
Broadcom. Using analog Phase-Locked Loop
(PLL) techniques, the device accepts a 25.00 MHz
clock or fundamental mode crystal input to
produce multiple output clocks of 25.0 MHz, two
125.0 MHz, 133.33 MHz, and a selectable
33.3/66.6 MHz clock. All output clocks are
frequency locked together. The ICS650-07B
outputs all have 0 ppm synthesis error.
Do not use the 125 MHz outputs to drive Gigabit
Ethernet SERDES. Instead, the 25 MHz clock
can be driven into our ICS601 in the X5 mode.
The ICS601 has low enough jitter and phase noise
for all popular SERDES.
Block Diagram
VDD GND
43
• Packaged in 20 pin narrow (150 mil) SSOP (QSOP)
• 25.00 MHz fundamental crystal or clock input
• Four fixed output clocks of 25 MHz, 133.33 MHz,
and two copies of 125 MHz
• One selectable output clock of 33.3 or 66.6 MHz
• Zero ppm synthesis error in all clocks
• PCI clock switching occurs within 1 µs
• Ideal for Broadcom’s BCM5600 chipset
• Full CMOS output swing
• Advanced, low power, sub-micron CMOS process
• 3.0 V to 5.5 V operating voltage
Output
Buffer
PCI CLK
PS
Clock Synthesis
and Control
Output
Buffer
125.00 MHz
Circuitry
Output
Buffer
125.00 MHz
25.00 MHz
crystal or clock
X1
X2
Clock
Buffer/
Crystal
Oscillator
Output
Buffer
Output
Buffer
133.33 MHz
25.00 MHz
OE (all outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
MD S 650-07B A
1
Revision 042600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com
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