AV9248F-151 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
Manufacturer
AV9248F-151
Integrated Circuit Systems
AV9248F-151 Datasheet PDF : 14 Pages
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ICS9248-151
Pin Descriptions
PIN NUMBER
1
2, 12, 19, 25,
30, 36, 40, 43
PIN NAME
VDDREF
GND
3
X1
4
X2
5
AVDD48MHz
FS3
6
48MHz
FS2
7
24_48MHz
8
AGND48MHz
9
PCICLK_F
20, 18, 17, 16, 14,
13, 11, 10
15
21, 22
27, 26, 23
24
28
29
31
PCICLK (7:0)
VDDPCI
FS (1:0)1, 2
AGPCLK (2:0)
VDDAGP
SCLK
SDATA
AVDD
32
PD#
33
34
35
37, 41
38, 39
42, 44, 45
46
47
48
PCI_STOP#1
CPU_STOP#
CPUCLK2/F
VDDLCPU
CPUCLK (1:0)
IOAPIC (2:0)
VDDLAPIC
FS41, 2
REF1
REF0
TYPE
DESCRIPTION
PWR Ref, XTAL power supply, nominal 3.3V
PWR Ground
IN
OUT
PWR
IN
OUT
IN
OUT
PWR
OUT
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Power for 24 & 48MHz output buffers and fixed PLL core.
Frequency select pin. Latched Input. Internal Pull-up to VDD
48MHz output clock
Frequency select pin. Latched Input. Internal Pull-up to VDD
24 or 48MHz output
Ground for 24 & 48MHz output buffers and fixed PLL core.
Free running PCI clock not affected by PCI_STOP# for power
management.
OUT PCI clock outputs. Syncheronous to CPU clocks with 1-2ns skew
PWR
IN
OUT
PWR
IN
I/O
PWR
IN
IN
IN
OUT
PWR
OUT
OUT
PWR
IN
OUT
OUT
Supply for PCICLK_F and PCICLK, nominal 3.3V
Frequency select pin. Latched Input. Internal Pull-up to VDD
AGP outputs defined as 2X PCI. These may not be stopped.
Power for AGP clocks
Clock input of I2C input, 5V tolerant input
Data pin for I2C circuitry 5V tolerant
Power for PLL core 3.3V
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are disabled
and the VCO and the crystal are stopped. The latency of the
power down will not be greater than 3ms.
Halts PCICLK clocks at logic 0 level, when input low (In mobile
mode, MODE=0)
This asynchronous input halts CPUCLKs at logic "0" level when
driven low.
CPUCLK either stoppable through CPU_STOP# or free running
depending on I2C selection , 0 = Free Running 1= Stoppable
Supply for CPU clocks 2.5V nominal
CPU clock outputs, Low if CPU_STOP#=Low
IOAPIC clock output. 14.318 MHz Powered by VDDLIOAPIC.
Supply for IOAPIC, 2.5V nominal
Frequency select pin. Latched Input
14.318 MHz reference clock.
14.318 Mhz reference clock.
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
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