ICS93705 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
Manufacturer
ICS93705 Datasheet PDF : 7 Pages
| |||
ICS9370 5
Recommended Operating Condition
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Analog/core supply
voltage
VDD, AVDD
2.3
2.5
2.7
Input voltage level
Input duty cycle
Input max jitter
VIL
VIH
IDC
ITCYC
-
VDD/2 + 0.5V
40
VDD/2 - 0.5V
-
60
500
UNITS
V
V
V
%
ps
Timing Requirements
TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Operating Clock Frequency1
Input Clock Duty Cycle1
Clock Stabilization1
freqop
dtin
tSTAB
from VDD = 2.5V to 1% target frequency
1. Guaranteed by design, not 100% tested in production.
MIN TYP MAX UNITS
66
170 MHz
40
60
%
100 µs
Switching Characteristics
TA = 0 - 70C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Absolute Jitter1
tjabs
66 MHz
100 / 125 / 133 / 167 MHz
Cycle to cycle Jitter1,2
Phase Error1
Output to output Skew1
tc-c
tpe
Ts k ew
66 MHz
100 / 125 / 133 / 167 MHz
with input clock 0-2.5V 0.8ns rise/fall
with input clock 0-2.5V 0.8ns rise/fall
50
35
-150 50
40
Low-to-high level Propagation
Delay Time, Bypass Mode1
tPLH
CLK_IN to any output, Load = 120W / 12 pF 4
4.5
Pulse Skew1
Duty Cycle (differential)1,3
Rise Time, Fall Time1
Tskewp
DC
no loads, 66 MHz to 167 MHz
49
50
tR, tF
Single-ended 20 - 80 %; Load = 120Ω / 12 pF 450
550
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting period.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formula: duty cycle = twH / tC, where the cycle time (tC) decreases as the frequency increases.
MAX
120
75
110
65
150
100
UNITS
ps
ps
ps
ps
6
ns
100 ps
51
%
950 ps
0418C—08/08 /02
5
Share Link: 