ICS93735 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
Manufacturer
ICS93735 Datasheet PDF : 7 Pages
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ICS93735
Recommended Operation Conditions
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Analog / Core Supply Voltag
Input Voltage Level
Output Differential Pair
Crossing Voltage
AVDD
VIN
VOC
66/100/133/166MHz, VDD=2.50V
2.3 2.5 2.7
V
2
2.5
3
V
1.23 1.25 1.32
V
Timing Requirements
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Operating Clock Frequency1 freqop Input Voltage level: 0-2.50V
Input Clock Duty Cycle1
Clock Stabilization1
dtin
tSTAB
from VDD = 2.5V to 1% target frequency
1. Guaranteed by design, not 100% tested in production.
MIN TYP MAX UNITS
22
340 MHz
40 50 60
%
100
µs
Switching Characteristics
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Cycle to cycle Jitter1,2
tc-c
66 MHz
100 / 125 / 133 MHz
46 52 63
27 33 40
Phase Error1
Output to output Skew1
tpe
Tskew
100MHz, input clock 0-2.5V, 0.8ns rise/fall
-113
input clock 0-2.5V, 0.8ns rise/fall
66
98
Low-to-high level Propagation
Delay Time, Bypass Mode1
tPLH
CLK_IN to any output,
100MHz, Load = 120 W / 12 pF
3.67
3.68
Pulse Skew1
Duty Cycle (Sign Ended)1,3
Tskew
DC
no loads, 66 MHz to 167MHz
50.2
51.3
Rise Time1
Fall Time1
tR
Single-ended 20-80 %; Load=120W/12pF 400 490 622
tF
Single-ended 20-80 %; Load=120W/12pF 435 579 711
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting period.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formular: duty_cycle=twH/tC, where the cycle time (tC)decreases as the frequency increases.
UNITS
ps
ps
ps
ns
ps
%
ps
ps
0579E—08/06/03
6
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