ICS932S208 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
ICS932S208 Datasheet PDF : 21 Pages
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ICS932S208
Programmable Timing Control HubTM for Next Gen P4TM Processor
General Description
ICS932S208 follows Intel CK409B Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS932S208 is driven with a 14.318MHz crystal. It generates CPU outputs
up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
X1
XTAL
X2
PLL2
Frequency
Dividers
SCLK
SDATA
Vtt_PWRGD#
PD#
FS_A
FS_B
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz, USB, DOT
REF (1:0)
CPUCLKT (3:0)
CPUCLKC (3:0)
SRCCLKT0
SRCCLKC0
3V66(4:0)
PCICLK (6:0)
PCICLKF (2:0)
I REF
Power Groups
Pin Number
VDD
GND
3
6
24
25
10,16 11,17
36
39
55
54
34
33
N/A
53
48, 42
45
Description
Xtal, Ref
3V66 [0:3]
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
48MHz, PLL
IREF
CPUCLK clocks
IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor
4
0743G—01/26/10
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