IDT71V432 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT71V432
Integrated Device Technology
IDT71V432 Datasheet PDF : 18 Pages
| |||
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Synchronous Write Function Truth Table(1)
Operation
GW
BWE
BW1
Read
H
H
X
Read
H
L
H
Write all Bytes
L
X
X
Write all Bytes
Write Byte 1(2)
Write Byte 2(2)
Write Byte 3(2)
Write Byte 4(2)
H
L
L
H
L
L
H
L
H
H
L
H
H
L
H
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
Commercial and Industrial Temperature Ranges
BW2
BW3
BW4
X
X
X
H
H
H
X
X
X
L
L
L
H
H
H
L
H
H
H
L
H
H
H
L
3104 tbl 08
Asynchronous Truth Table(1)
Operation(2)
OE
ZZ
I/O Status
Read
L
L
Data Out (I/O0 - I/O31)
Read
H
L
High-Z
Write
X
L
High-Z — Data In (I/O0 - I/O31)
Deselected
X
L
High-Z
Sleep
X
H
High-Z
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Power
Active
Active
Active
Standby
Sleep
3104 tbl 09
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
A1 A0
A1 A0
First Address
00
0
1
Second Address
0
1
00
Third Address
10
11
Fourth Address(1)
11
10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Sequence 3
A1 A0
10
11
00
0
1
Sequence 4
A1 A0
1
1
10
0
1
0
0
3104 tbl 10
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
A1 A0
A1 A0
First Address
0
0
0
1
Second Address
0
1
10
Third Address
Fourth Address(1)
10
1
1
11
00
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.472
Sequence 3
A1 A0
10
1
1
0
0
0
1
Sequence 4
A1 A0
11
00
0
1
10
3104 tbl 11
Share Link: