IDT72V3634 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT72V3634

3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol

Name

I/O

Description

A0-A35

AEA

AEB

AFA

AFB

B0-B35

BE/FWFT

Port A Data

Port A Almost-

Empty Flag

Port B Almost-

Empty Flag

Port A Almost-

Full Flag

Port B Almost-

Full Flag

Port A Data

Big-Endian/

First Word

Fall Through

Select

BM

CLKA

Bus-Match

Select

(Port B)

Port A Clock

CLKB

Port B Clock

CSA

CSB

EFA/ORA

Port A Chip

Select

Port B Chip

Select

Port A Empty/

Output Ready

Flag

EFB/ORB

Port B Empty/

Output Ready

Flag

ENA

ENB

FFA/IRA

FFB/IRB

Port A Enable

Port B Enable

Port A Full/

Input Ready

Flag

Port B Full/

Input Ready

Flag

I/O 36-bit bidirectional data port for side A.

O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is

less than or equal to the value in the Almost-Empty A Offset register, X2.

O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is

less than or equal to the value in the Almost-Empty B Offset register, X1.

O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in

FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.

O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in

FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.

I/O 36-bit bidirectional data port for side B.

I This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this

case, depending on the bus size, the most significant byte or word on Port A is read from Port B first

(A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Little-Endian operation.

In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B data flow) or

written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH on

FWFT selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has

been selected, the level on FWFT must be static throughout device operation.

I A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A

LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian

arrangement for Port B. The level of BM must be static throughout device operation.

I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous

or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH

transition of CLKA.

I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous

or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH transition

of CLKB.

I CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35

outputs are in the high-impedance state when CSA is HIGH.

I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. The

B0-B35 outputs are in the high-impedance state when CSB is HIGH.

O This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates whether

or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the

presence of valid data on A0-A35 outputs, available for reading. EFA/ORA is synchronized to the LOW-to-

HIGH transition of CLKA.

O This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates whether

or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the

presence of valid data on the B0-B35 outputs, available for reading. EFB/ORB is synchronized to the LOW-to-

HIGH transition of CLKB.

I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.

I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.

O This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates

whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates

whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the

LOW-to-HIGH transition of CLKA.

O This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates whether

or not the FIFO2 memory is full. In theFWFT mode, the IRB function is selected. IRB indicates whether or

not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH

transition of CLKB.

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