IDT72V3634 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT72V3634 Datasheet PDF : 34 Pages
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IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES O. SUPPLY
VOLTAGE AND OPERATING .REE-AIR TEMPERATURE, CL = 30p.
Commercial: VCC = 3.3V +/- 0.30V; for 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V ; TA = 0°C to +70°C; JEDEC JESD8-A compliant
IDT72V3624L10(1)
IDT72V3634L10(1)
IDT72V3644L10(1)
IDT72V3624L15
IDT72V3634L15
IDT72V3644L15
Symbol
Parameter
Min. Max. Min. Max. Unit
tA
Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35
2
6.5
2
10
ns
tWFF
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to FFB/IRB
2
6.5
2
8
ns
tREF
Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to EFB/ORB
1
6.5
1
8
ns
tPAE
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB
1
6.5
1
8
ns
tPAF
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
1
6.5
1
8
ns
tPMF
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑
0
6.5
0
8
ns
to MBF2 LOW or MBF1 HIGH
tPMR
Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3)
2
8
2
10
ns
tMDV
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 valid
2
6.5
2
10
ns
tRSF
Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and
1
10
1
15
ns
MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, and MBF2
HIGH
tEN
Enable Time, CSA or W/RA LOW to A0-A35 Active and CSB LOW and W/RB
2
6
2
10
ns
HIGH to B0-B35 Active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB
HIGH or W/RB LOW to B0-B35 at HIGH impedance
1
6
1
8
ns
NOTES:
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0° to +70°C; JEDEC JESD8-A compliant.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Industrial temperature range is available by special order.
9
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