IDT7M1002 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT7M1002

16K x 32 CMOS DUAL-PORT STATIC RAM MODULE

Integrated Device Technology 

IDT7M1002

16K x 32 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE WITH BUSY INPUT (M/S ≤ VIL)

R/W

BUSY

tWP

tWB

tWH

DATAINR

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TIMING WAVEFORM OF BUSY ARBITRATION (CS CONTROLLED TIMING)(1)

ADDR "A"

AND "B"

ADDRESS MATCH

CS "A"

CS "B"

BUSY "B"

tAPS (2)

tBAC

tBDC

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TIMING WAVEFORM OF BUSY ARBITRATION (CONTROLLED BY ADDRESS MATCH TIMING(1)

ADDR "A"

ADDR"B"

BUSY "B"

tAPS (2)

ADDRESS "N"

MATCHING ADDRESS "N"

tBAA

tBDA

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NOTES:

1. All timing is the same for the left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.

7.02

10

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