IDTCV109E View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDTCV109E

CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

Integrated Device Technology 

IDTCV109E

CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

COMMERCIAL TEMPERATURE RANGE

ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT

PARAMETERS

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VIH

3.3V Input HIGH Voltage

3.3V ± 5%

2

—

VDD + 0.3

V

VIL

3.3V Input LOW Voltage

IIH

Input HIGH Current

3.3V ± 5%

VIN = VDD

VSS - 0.3

—

0.8

V

–5

—

5

µA

IIL1

Input LOW Current

VIN = 0V, inputs with no pull-up resistors

–5

—

—

µA

IIL2

Input LOW Current

VIN = 0V, inputs with pull-up resistors

–200

—

—

µA

IDD3.3OP

IDD3.3PD

Operating Supply Current

Powerdown Current

FI

Input Frequency(2)

LPIN

Pin Inductance(3)

Full active, CL = full load

All differential pairs driven

All differential pairs tri-stated

VDD = 3.3V

—

—

400

mA

—

—

70

mA

—

—

12

— 14.31818 —

MHz

—

—

7

nH

CIN

COUT

CINX

TSTAB

Input Capacitance(3)

Clock Stabilization(3,4)

Modulation Frequency(3)

TDRIVE_SRC(3)

TDRIVE_PD#(3)

TFALL_PD#(3)

TRISE_PD#(4)

TDRIVE_CPU_Stop#(3)

TFALL_CPU_Stop#(3)

TRISE_CPU_Stop#(4)

Logic inputs

Output pin capacitance

X1 and X2 pins

From VDD power-up or de-assertion of PD# to first clock

Triangular modulation

SRC output enable after PCI_Stop# de-assertion

CPU output enable after PD# de-assertion

Fall time of PD#

Rise time of PD#

CPU output enable after CPU_Stop# de-assertion

Fall time of PD#

Rise time of PD#

—

—

5

—

—

6

pF

—

—

5

—

—

1.8

ms

30

—

33

KHz

—

—

15

ns

—

—

300

us

—

—

5

ns

—

—

5

ns

—

—

10

us

—

—

5

ns

—

—

5

ns

NOTES:

1. Available to CV104, CV105, CV107, and CV109.

2. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.

3. This parameter is guaranteed by design, but not 100% production tested.

4. See TIMING DIAGRAMS for timing requirements.

15

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