IDTCV125 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDTCV125 Datasheet PDF : 24 Pages
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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
BYTE 3
Bit
0
1
2
3
4
5
6
7
Output(s) Affected
Reserved
SRC1
SRC2
SRC3
SRC4
SRC5
SRC6
SRC7
Description / Function
Allow controlled by
PCI_STOP# assertion
0
Free running, not
affected by PCI_STOP#
COMMERCIAL TEMPERATURE RANGE
1
Stopped with
PCI_STOP#
Type
Power On
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
BYTE 4
Bit
0
1
2
3
4
5
6
7
Output(s) Affected
CPU0, CPU0#
CPU1, CPU1#
CPU2, CPU2#
PCIF0
PCIF1
Reserved
DOT96
Reserved
Description / Function
Allow control of CPU0
with assertion of CPU_STOP#
Allow control of CPU1
with assertion of CPU_STOP#
Allow control of CPU2
with assertion of CPU_STOP#
Allow controlled by
PCI_STOP# assertion
0
Not stopped
by CPU_STOP#
Not stopped
by CPU_STOP#
Not stopped
by CPU_STOP#
Not stopped
by PCI_STOP#
DOT96 power down drive mode Driven in power down
1
Stopped with
CPU_STOP#
Stopped with
CPU_STOP#
Stopped with
CPU_STOP#
Stopped with
PCI_STOP#
Tristate
Type
Power On
RW
1
RW
1
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
BYTE 5
Bit
Output(s) Affected
Description / Function
0
1
Type
0
CPU0, CPU0#
CPU0 PD drive mode
Driven in power down Tristate in power down RW
1
CPU1, CPU1#
CPU1 PD drive mode
Driven in power down Tristate in power down RW
2
CPU2, CPU2#
CPU2 PD drive mode
Driven in power down Tristate in power down RW
3
SRC[7:1], SRC[7:1]#
SRC PD drive mode
Driven in power down Tristate in power down RW
4
CPU0, CPU0#
CPU0 CPU_STOP drive mode Driven in CPU_STOP# Tristatewhenstopped
RW
5
CPU1, CPU1#
CPU1 CPU_STOP drive mode Driven in CPU_STOP# Tristatewhenstopped
RW
6
CPU2, CPU2#
CPU2 CPU_STOP drive mode Driven in CPU_STOP# Tristatewhenstopped
RW
7
SRC[7:1], SRC[7:1]#
SRC PCI_STOP drive mode
Driven in PCI_STOP Tristatewhenstopped
RW
Power On
0
0
0
0
0
0
0
0
7
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