IDTCV193 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDTCV193 Datasheet PDF : 21 Pages
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IDTCV193
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
N-PROGRAMMING PROCEDURE
• Byte 16 bit 3 has to be "1". This bit will decode the power on latched
value of pins 4, 5 (see CFG table 1).
.• User writes the desired CPU frequency in HEX form into CPUN [8:0],
Byte 16, 17.
• User writes the desired SRC frequency in HEX form into PN [7:0], Byte
18.
CONTROL REGISTERS
BYTE 0
Bit Output(s) Affected
7
FSC
6
FSB
5
FSA
4
iAMT_EN
3
Reserved
2
Reserved
1 SRC2/SATA source
0
PD_Restore
Description/Function
Latched FSC
Latched FSB
Latched FSA
iAMT Mode
SMBUS control registers
setting
after the power down
0
Legacy Mode
PLL4
Power on default, With
some exceptions
NOTES:
1. Sticky 1, can only be reset by power off.
1
Enabled
PLL2
Save register
contents
Type
R
R
R
RW
RW
RW
RW
Power On
Latched Value
Latched Value
Latched Value
HW M1 setting(1)
0
0
SATA_SEL latch
RW
1
BYTE 1
Bit Output(s) Affected
7
SRC0_sel
6
PLL1_SSC_DC
5
PLL4_SSC_DC
4
Reserved
3
Reserved
2
25MHz_0
1
25MHz_1
0
PCI
Description/Function
Pin13/14 mode select
SSC mode selection
SSC mode selection
PD# free run control
PD# free run control
0
SRC0
Down spread
Down spread
Disabled
Disabled
PLL2
1
DOT96
Center spread
Center spread
Free run
Free run
PLL4
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
1
0
0
0
1
1
1
BYTE 2
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
REF
USB_48
PCIF5
PCI4
PCI3
PCI2
PCI1
PCI0
Description/Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
0
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
1
1
1
1
1
1
1
1
IDT CONFIDENTIAL
7
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