IDTCV110JPVG View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDTCV110JPVG

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Integrated Device Technology 

IDTCV110J

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

BYTE 4

Bit

0

1

2

3

4

5

6

7

Output(s) Affected

Reserved

Reserved

Reserved

PCIF0

PCIF1

PCIF2

DOT96

Reserved

Description / Function

Allow controlled by software

PCI_STOP, byte 6, bit 3, assertion

DOT96 power down drive mode

0

Not stopped

by PCI_STOP

Driven in power down

COMMERCIAL TEMPERATURE RANGE

1

Type

RW

RW

RW

RW

Stopped with

RW

PCI_STOP

RW

Tristate

RW

Power On

1

1

1

0

0

0

0

0

BYTE 5

Bit

0

1

2

3

4

5

6

7

Output(s) Affected

CPU0, CPU0#

CPU1, CPU1#

CPU2, CPU2#

SRC[7:1], SRC[7:1]#

Reserved

Reserved

Reserved

SRC[7:1], SRC[7:1]#

Description / Function

CPU0 PWRDWN drive mode

CPU1 PWRDWN drive mode

CPU2 PWRDWN drive mode

SRC PWRDWN drive mode

SRC PCI_STOP drive mode

0

1

Type

Driven in power down Tristate in power down RW

Driven in power down Tristate in power down RW

Driven in power down Tristate in power down RW

Driven in power down Tristate in power down RW

Driven in PCI_STOP Tristatewhenstopped

RW

Power On

0

0

0

0

0

0

0

0

BYTE 6

Bit

Output(s) Affected

Description / Function

0

1

Type

0

CPU[2:0]

FSA latched value on power up

R

1

CPU[2:0]

FSB latched value on power up

R

2

CPU[2:0]

FSC latched value on power up

R

3

PCI, SRC

Software PCI_STOP control for Stop all PCI, PCIF, and Software STOP

RW

PCI and SRC CLK

SRC which can be stopped

Disabled

by PCI_STOP#

4

REF

REF drive strength

1x drive

2x drive

5

Reserved

6

Test clock mode entry control

Normal operation

Test mode, controlled

RW

by Byte 6, Bit 7

7

CPU, SRC, PCI

Only valid when Byte 6, Bit 7

Hi-Z

PCIF, REF,

is HIGH

USB48, DOT96

REF/N

Power On

1

1

0

0

0

7

Share Link: