IDTCV115-2PVG View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDTCV115-2PVG Datasheet PDF : 19 Pages
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IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
BYTE 28
Bit
Output(s) Affected
Description / Function
0
7
TCN7
6
TCN6
5
TCN5
Turbo CPU PLL N setting
4
TCN4
CPU Frequency = N * Resolution
3
TCN3
(see Resolution table)
2
TCN2
1
TCN1
0
TCN0 (LSB)
COMMERCIAL TEMPERATURE RANGE
1
Type
Power On
RW
1
RW
0
RW
0
RW
1
RW
0
RW
1
RW
1
RW
0
BYTE 29
Bit
Output(s) Affected
Description / Function
0
7
TPN8 (MSB)
6
TPN7
5
TPN6
Turbo SRC PLL N setting
4
TPN5
SRC Frequency = N * Resolution
3
TPN4
Resolution = 0.666667
2
TPN3
1
TPN2
0
TPN1
1
Type
Power On
0
1
0
0
1
0
1
1
BYTE 30
Bit
7
6
5
Output(s) Affected
TPN0 (LSB)
TCN28
Description / Function
Test Mode entry control
4
Only valid when Byte6 bit5 is high
3
PCI4/Turbo 1
PCI4/Turbo Mode select
2
Turbo 1
1
Test_scl
On chip test mode enable
0
Test_hiz
CLK outputs enable
0
Normal operation
Hi-Z
Turbo 1
Disable
normal
normal
1
Type
Test mode,
controlled by byte 30 bit 4
REF/N mode
PCI4
RW
Enable
RW
SCLK=1, CLK outputs=1 RW
SCLK=0, CLK outputs=0
CLK outputs=Tristate
RW
Power On
0
0
0
0
0
0
0
0
BYTE 31
Bit
Output(s) Affected
Description / Function
0
7
TCN27
6
TCN26
5
TCN25
4
TCN24
Turbo CPU PLL N setting
3
TCN23
2
TCN22
1
TCN21
0
TCN20
11
1
Type
Power On
1
0
0
1
0
1
1
0
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