IDTCV115-2PV View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDTCV115-2PV Datasheet PDF : 19 Pages
| |||
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
PIN CONFIGURATION
VDD_PCI 1
VSS_PCI 2
PCI2 3
PCI3 4
(1)
PCI4/Turbo1 5
VSS_PCI 6
VDD_PCI 7
PCIF0/ITP_EN 8
PCIF1 9
PCIF2 10
VDD_48 11
FS_B/USB48MHz 12
VSS_48 13
DOT_96 14
DOT_96# 15
(2) VTT_PWRGD/PWRDWN#
16
SRCT1 17
SRCC1 18
VDD_SRC 19
VSS 20
SRCT2 21
SRCC2 22
SRCT3 23
SRCC3 24
VSS_GND 25
SRCT4_SATA 26
SRCC4_SATA 27
VDD_SRC 28
56 PCI1
55 PCI0
54 FS_A(REF1/PCI5)(3)
53 VDD_suspend
52 FS_C/REF0
51 VSS_REF
50 XTAL_IN
49 XTAL_OUT
48 VDD_REF
47 SCL(2)
46 SDA(2)
45 CPUT0
44 CPUC0
43 VDD_CPU
42 CPUT1
41 CPUC1
40 VSS_CPU
39 IREF
38 Reset#
37 Turbo2 (4)
36 CPU2_ITP/SRCT7
35 CPU2_ITP/SRCC7
34 VDD_SRC
33 SRCT6
32 SRCC6
31 SRCT5
30 SRCC5
29 VSS_SRC
COMMERCIAL TEMPERATURE RANGE
TEST MODE SELECT(1)
If TEST_SEL sampled above 2V at VTT_PWRGD active LOW
Pin38
(test_mode)
CPU
SRC PCI/F REF
1
REF/N REF/N REF/N REF
0
Hi-Z
Hi-Z Hi-Z Hi-Z
DOT96
REF/N
Hi-Z
USB
REF/N
Hi-Z
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between
the Hi-Z and REF/N,
ITP_EN
ITP_EN
1
0
pin 35
CPUC2_ITP
SRCC7
pin 36
CPUT_ITP
SRCT7
NOTES:
1. After power on, pin 5 is tristate (see Byte 30 and Byte 2).
2. ~ 130KΩ internal pull-up.
3. After power on, REF1/PCI5 is tristate (see Byte 1).
4. Disabled at power on.
SSOP
TOP VIEW
HW FREQUENCY SELECTION TABLE
FSC, B, A
CPU
SRC4_SATA SRC[3:1], SCR[7:5]
PCI
101
100
100
100
33.3
001
133
100
100
33.3
011
166
100
100
33.3
010
200
100
100
33.3
000
266
100
100
33.3
100
333
100
100
33.3
110
400
100
100
33.3
111
Reserve
100
100
33.3
USB
DOT
REF
48
96
14.318
48
96
14.318
48
96
14.318
48
96
14.318
48
96
14.318
48
96
14.318
48
96
14.318
48
96
14.318
2
Share Link: 