IDTCV115CPVG View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDTCV115CPVG Datasheet PDF : 19 Pages
| |||
IDTCV115C
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number
Name
Type
1
VDD_PCI
PWR
2
VSS_PCI
GND
3
PCI2
OUT
4
PCI3
OUT
5
PCI4
OUT
6
VSS_PCI
GND
7
VDD_PCI
PWR
8
PCIF0/ITP_EN
I/0
9
PCIF1
OUT
10
PCIF2
OUT
11
VDD_48
PWR
12
USB48
OUT
13
VSS_48
GND
14
DOT_96T
OUT
15
DOT_96C
OUT
16
**VTT_PWRGD#/PWRDWN
I/O
17
SRCT1
OUT
18
SRCC1
OUT
19
VDD_SRC
PWR
20
VSS
GND
21
SRCT2
OUT
22
SRCC2
OUT
23
SRCT3
OUT
24
SRCC3
OUT
25
VSS
GND
26
SRCT4_SATA
OUT
27
SRCC4_SATA
OUT
28
VDD_SRC
PWR
29
VSS_SRC
GND
30
SRCC5
OUT
31
SRCT5
OUT
32
SRCC6
OUT
33
SRCT6
OUT
34
VDD_SRC
PWR
35
CPUC2_ITP/ SRCC7 OUT
36
CPUT2_ITP/ SRCT7
OUT
37
FS_C/Test_Sel
I/O
38
FS_B/ Test_Mode
I/O
39
IREF
OUT
40
VSS
GND
41
CPUC1
OUT
42
CPUT1
OUT
43
VDD_CPU
PWR
44
CPUC0
OUT
45
CPUT0
OUT
46
*SDA
I/O
Description
3.3V
GND
PCI clock
PCI clock
PCI clock
GND
3.3V
PCI clock, free running. CPU_2 select (sampled at VTT_PWRGD# assertion), HIGH = CPU_2.
PCI clock,
PCI clock,
3.3V
48MHz clock
GND
96MHz 0.7V current mode differential clock output
96MHz 0.7V current mode differential clock output
3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL and
PCIF_0/ITP_EN inputs. After VTT_PWRGD# assertion, becomes a real-time input for asserting power
down (active high). Internal pull LOW.
Differential Serial reference clock
Differential Serial reference clock
3.3V
GND
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
GND
SATA clock
SATA clock
3.3V
GND
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
3.3V
Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRC_7
Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRC_7
CPU frequency selection. Selects test mode if pulled above 2V when VTT_PWRGD# is asserted.
CPU frequency selection. In test mode, 1=Hi-Z, 0=REF/N.
Reference current for differential output buffer
GND
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
3.3V
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
SMBus data
3
Share Link: 