IDTCV115C View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDTCV115C Datasheet PDF : 19 Pages
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IDTCV115C
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number
Name
Type
47
*SCL
IN
48
VDD_REF
PWR
49
XTAL_OUT
OUT
50
XTAL_IN
IN
51
VSS_REF
GND
52
REF0
OUT
53
VDD_Suspend
PWR
54
FS_A
IN
55
PCI0
OUT
56
PCI1
OUT
Description
SMBus CLK
3.3V
Xtal output
Xtal input
GND
14.318 MHz reference clock output
In the power down mode, supply 3.3V to SM control registers, <1mA. In the normal operation, regular
VDD.
CPU frequency selection
PCI clock
PCI clock
SM PROTOCOL
INDEX BLOCK WRITE PROTOCOL
Bit # of bits From
Description
1
1
Master
Start
2-9
8
Master
D2h
10
1
Slave
Ack (Acknowledge)
11-18
8
Master
Register offset byte (starting byte)
19
1
Slave
Ack (Acknowledge)
20-27
8
Master
Byte count, N, (0 is not valid
28
1
Slave
Ack (Acknowledge)
29-36
8
Master
first data byte (Offset data byte)
37
1
Slave
Ack (Acknowledge)
38-45
8
Master
2nd data byte
46
1
Slave
Ack (Acknowledge)
:
Master
Nth data byte
Slave
Acknowledge
Master
Stop
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Bit # of bits
1
1
2-9
8
10
1
11-18
8
19
1
20
1
21-28
8
29
1
30-37
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
38
1
39-46
8
47
1
48-55
8
Master
Slave
Master
Slave
Master
Slave
Master
Description
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3h
Ack (Acknowledge)
Byte count, N (block read back of N
bytes), Byte 8
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
4
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