IDT82V3358 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT82V3358

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

List of Tables

Table 1: Pin Description ............................................................................................................................................................................................. 13

Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 17

Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 18

Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 19

Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 21

Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 22

Table 7: Input Clock Selection for T4 Path ................................................................................................................................................................ 22

Table 8: External Fast Selection ................................................................................................................................................................................ 22

Table 9: ‘n’ Assigned to the Input Clock ..................................................................................................................................................................... 23

Table 10: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 23

Table 11: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 24

Table 12: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 24

Table 13: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 25

Table 14: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 26

Table 15: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 27

Table 16: T0 DPLL Operating Mode Control ............................................................................................................................................................... 28

Table 17: T4 DPLL Operating Mode Control ............................................................................................................................................................... 30

Table 18: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 30

Table 19: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 31

Table 20: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 32

Table 21: Holdover Frequency Offset Read ................................................................................................................................................................ 32

Table 22: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 33

Table 23: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 35

Table 24: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 36

Table 25: Outputs on OUT1 ~OUT4 if Derived from T0/T4 DPLL Outputs ................................................................................................................. 36

Table 26: Outputs on OUT1 ~OUT4 if Derived from T0 APLL .................................................................................................................................... 37

Table 27: Outputs on OUT3 & 4 if Derived from T4 APLL ........................................................................................................................................... 38

Table 28: Outputs on OUT1 & OUT2 if Derived from T4 APLL ................................................................................................................................... 39

Table 29: Frame Sync Input Signal Selection .............................................................................................................................................................. 40

Table 30: Synchronization Control ............................................................................................................................................................................... 40

Table 31: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 41

Table 32: Related Bit / Register in Chapter 3.14 ......................................................................................................................................................... 42

Table 33: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 46

Table 34: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 46

Table 35: JTAG Timing Characteristics ....................................................................................................................................................................... 47

Table 36: Register List and Map .................................................................................................................................................................................. 48

Table 37: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 116

Table 38: Thermal Data ............................................................................................................................................................................................. 116

Table 39: Absolute Maximum Rating ......................................................................................................................................................................... 117

Table 40: Recommended Operation Conditions ........................................................................................................................................................ 117

Table 41: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 118

Table 42: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 118

Table 43: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 118

Table 44: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 118

Table 45: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 120

Table 46: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 121

Table 47: Output Clock Jitter Generation .................................................................................................................................................................. 123

Table 48: Output Clock Phase Noise ......................................................................................................................................................................... 124

List of Tables

6

May 19, 2009

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