IDT82V3380 View Datasheet(PDF) - Integrated Device Technology
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IDT82V3380 Datasheet PDF : 175 Pages
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IDT82V3380
SYNCHRONOUS ETHERNET WAN PLL
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 34
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 34
3.10.1.5 Holdover Mode ................................................................................................................................................................. 34
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 35
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 35
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 35
3.10.1.5.4 Manual ........................................................................................................................................................... 35
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 35
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 35
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 35
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 35
3.10.2.2 Locked Mode .................................................................................................................................................................... 35
3.10.2.3 Holdover Mode ................................................................................................................................................................. 35
3.11 T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 37
3.11.1 PFD Output Limit ............................................................................................................................................................................ 37
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 37
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 37
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 37
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 37
3.11.5.1 T0 Path ............................................................................................................................................................................. 37
3.11.5.2 T4 Path ............................................................................................................................................................................. 38
3.12 T0 / T4 APLL ................................................................................................................................................................................................. 39
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 39
3.13.1 Output Clocks ................................................................................................................................................................................. 39
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 44
3.14 MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 46
3.15 INTERRUPT SUMMARY ............................................................................................................................................................................... 47
3.16 T0 AND T4 SUMMARY ................................................................................................................................................................................. 47
3.17 POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 48
4 TYPICAL APPLICATION ................................................................................................................................................. 49
4.1 MASTER / SLAVE APPLICATION ............................................................................................................................................................... 49
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 50
5.1 EPROM MODE .............................................................................................................................................................................................. 51
5.2 MULTIPLEXED MODE .................................................................................................................................................................................. 52
5.3 INTEL MODE ................................................................................................................................................................................................. 54
5.4 MOTOROLA MODE ...................................................................................................................................................................................... 56
5.5 SERIAL MODE .............................................................................................................................................................................................. 58
6 JTAG ................................................................................................................................................................................ 60
7 PROGRAMMING INFORMATION .................................................................................................................................... 61
7.1 REGISTER MAP ............................................................................................................................................................................................ 61
7.2 REGISTER DESCRIPTION ........................................................................................................................................................................... 67
7.2.1 Global Control Registers ............................................................................................................................................................... 67
7.2.2 Interrupt Registers ......................................................................................................................................................................... 76
7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 81
7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ......................................................................................... 104
7.2.5 T0 / T4 DPLL Input Clock Selection Registers ........................................................................................................................... 118
7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 122
7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 124
7.2.8 Output Configuration Registers .................................................................................................................................................. 138
7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 148
7.2.10 Synchronization Configuration Registers ................................................................................................................................. 150
8 THERMAL MANAGEMENT ........................................................................................................................................... 151
8.1 JUNCTION TEMPERATURE ...................................................................................................................................................................... 151
Table of Contents
4
May 19, 2009
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