IDT82V3380 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT82V3380

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

List of Figures

Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11

Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12

Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 21

Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 23

Figure 5. External Fast Selection ................................................................................................................................................................................ 25

Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 26

Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 32

Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 33

Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 44

Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 44

Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 45

Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 45

Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 46

Figure 14. IDT82V3380 Power Decoupling Scheme ................................................................................................................................................... 48

Figure 15. Typical Application ...................................................................................................................................................................................... 49

Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 51

Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 52

Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 53

Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 54

Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 55

Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 56

Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 57

Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 58

Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 58

Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 59

Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 60

Figure 27. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................. 152

Figure 28. 64 kHz + 8 kHz Signal Structure .............................................................................................................................................................. 154

Figure 29. 64 kHz + 8 kHz + 0.4 kHz Signal Structure .............................................................................................................................................. 154

Figure 30. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Input Level ................................................................................................................ 154

Figure 31. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Output Level ............................................................................................................. 154

Figure 32. AMI Input / Output Port Line Termination (Recommended) ..................................................................................................................... 155

Figure 33. Recommended PECL Input Port Line Termination .................................................................................................................................. 157

Figure 34. Recommended PECL Output Port Line Termination ................................................................................................................................ 157

Figure 35. Recommended LVDS Input Port Line Termination .................................................................................................................................. 159

Figure 36. Recommended LVDS Output Port Line Termination ................................................................................................................................ 159

Figure 37. Example of Single-Ended Signal to Drive Differential Input ..................................................................................................................... 160

Figure 38. Output Wander Generation ...................................................................................................................................................................... 164

Figure 39. Input / Output Clock Timing ...................................................................................................................................................................... 165

Figure 40. 100-Pin EQG Package Dimensions (a) (in Millimeters) ............................................................................................................................ 172

Figure 41. 100-Pin EQG Package Dimensions (b) (in Millimeters) ............................................................................................................................ 173

Figure 42. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters) .............................................................................................. 174

List of Figures

8

May 19, 2009

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