IDT82V3385 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT82V3385

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

IDT82V3385

SYNCHRONOUS ETHERNET WAN PLL

Table 49: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 127

Table 50: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 127

Table 51: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 127

Table 52: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 129

Table 53: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 130

Table 54: Output Clock Jitter Generation .................................................................................................................................................................. 132

Table 55: Output Clock Phase Noise ......................................................................................................................................................................... 133

Table 56: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 133

Table 57: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 133

Table 58: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 133

Table 59: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 133

Table 60: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 134

Table 61: T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 134

Table 62: Input/Output Clock Timing 3 ...................................................................................................................................................................... 136

Table 63: Output Clock Timing .................................................................................................................................................................................. 137

List of Tables

7

May 14, 2010

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