IDT82V3385 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT82V3385

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

List of Figures

Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11

Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12

Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 20

Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 21

Figure 5. External Fast Selection ................................................................................................................................................................................ 23

Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 24

Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 30

Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 31

Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 41

Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 41

Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 42

Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 42

Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 43

Figure 14. IDT82V3385 Power Decoupling Scheme ................................................................................................................................................... 45

Figure 15. Typical Application ...................................................................................................................................................................................... 46

Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 47

Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 48

Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 49

Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 51

Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 52

Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 53

Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 54

Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 55

Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 55

Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 56

Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 57

Figure 27. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................. 125

Figure 28. Recommended PECL Input Port Line Termination .................................................................................................................................. 128

Figure 29. Recommended PECL Output Port Line Termination ................................................................................................................................ 128

Figure 30. Recommended LVDS Input Port Line Termination .................................................................................................................................. 130

Figure 31. Recommended LVDS Output Port Line Termination ................................................................................................................................ 130

Figure 32. Example of Single-Ended Signal to Drive Differential Input ..................................................................................................................... 131

Figure 33. Output Wander Generation ...................................................................................................................................................................... 134

Figure 34. Input / Output Clock Timing ...................................................................................................................................................................... 135

Figure 35. 100-Pin EQG Package Dimensions (a) (in Millimeters) ............................................................................................................................ 142

Figure 36. 100-Pin EQG Package Dimensions (b) (in Millimeters) ............................................................................................................................ 143

Figure 37. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters) .............................................................................................. 144

List of Figures

8

May 14, 2010

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