IDT82V3399 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT82V3399

SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588

Integrated Device Technology 

IDT82V3399 PRODUCT BRIEF

SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588

DESCRIPTION

The IDT82V3399 is an integrated, single-chip solution for the Syn-

chronous Equipment Timing Source for Stratum 3, 4E, 4, SMC, EEC-

Option1, EEC-Option2 clocks in SONET / SDH / Synchronous Ethernet

equipment, DWDM and Wireless base station.

The device supports several types of input clock sources: recovered

clock from Synchronous Ethernet, STM-N or OC-n, PDH network syn-

chronization timing and external synchronization reference timing.

The device consists of T0 and T4 paths. The T0 path is a high quality

and highly configurable path to provide system clock for node timing

synchronization within a SONET / SDH / Synchronous Ethernet network.

The T4 path is simpler and less configurable for equipment synchroniza-

tion. The T4 path locks independently from the T0 path or locks to the T0

path.

An input clock is automatically or manually selected for T0 and T4

path. Both the T0 and T4 paths support three primary operating modes:

Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to

the master clock. In Locked mode, the DPLL locks to the selected input

clock. In Holdover mode, the DPLL resorts to the frequency data

acquired in Locked mode. Whatever the operating mode is, the DPLL

gives a stable performance without being affected by operating condi-

tions or silicon process variations.

There are 2 high performance APLLs that can be used for low jitter

SONET and Ethernet Clocks

The device provides programmable DPLL bandwidths: 0.5 mHz to

560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different

settings cover all SONET / SDH clock synchronization requirements.

A highly stable input is required for the master clock in different appli-

cations. The master clock is used as a reference clock for all the internal

circuits in the device. It can be calibrated within ±741 ppm.

All the read/write registers are accessed through a microprocessor

interface. The device supports I2C and serial microprocessor interface

modes.

In general, the device can be used in Master/Slave application. In

this application, two devices should be used together to enable system

protection against single chip failure.

Description

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March 5, 2012

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