IMX51 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

IMX51

i.MX51 Applications Processors for Consumer and Industrial Products

Freescale Semiconductor 

Features

Table 2. i.MX51 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name Subsystem

Brief Description

SJC

Secure JTAG System

JTAG manipulation is a known hacker’s method of executing unauthorized

Interface

Control

program code, getting control over secure applications, and running code in

Peripherals privileged modes. The JTAG port provides a debug access to several hardware

blocks including the ARM processor and the system bus.

The JTAG port must be accessible during platform initial laboratory bring-up,

manufacturing tests and troubleshooting, as well as for software debugging by

authorized entities. However, in order to properly secure the system,

unauthorized JTAG usage should be strictly forbidden.

SPBA

SPDIF

SRTC

SSI-1

SSI-2

SSI-3

TVE

TZIC

In order to prevent JTAG manipulation while allowing access for manufacturing

tests and software debugging, the i.MX51 processor incorporates a mechanism

for regulating JTAG access. The i.MX51Secure JTAG Controller provides four

different JTAG security modes that can be selected via e-fuse configuration.

Shared

Peripheral

Bus Arbiter

System

Control

Peripherals

SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP bus)

arbiter.

Sony Philips

Digital

Interface

Multimedia

Peripherals

A standard digital audio transmission protocol developed jointly by the Sony and

Philips corporations. Only the transmitter functionality is supported.

Secure Real Security

Time Clock

The SRTC incorporates a special System State Retention Register (SSRR) that

stores system parameters during system shutdown modes. This register and all

SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The

NVCC_SRTC_POW can be energized even if all other supply rails are shut

down. This register is helpful for storing warm boot parameters. The SSRR also

stores the system security state. In case of a security violation, the SSRR mark

the event (security violation indication).

I2S/SSI/AC97 Connectivity

Interface

Peripherals

The SSI is a full-duplex synchronous interface used on the i.MX51 processor to

provide connectivity with off-chip audio peripherals. The SSI supports a wide

variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to

24 bits per word), and clock/frame sync options.

Each SSI has two pairs of 8x24 FIFOs and hardware support for an external

DMA controller in order to minimize its impact on system performance. The

second pair of FIFOs provides hardware interleaving of a second audio stream,

which reduces CPU overhead in use cases where two timeslots are being used

simultaneously.

TV Encoder Multimedia

The TVE is implemented in conjunction with the Image Processing Unit (IPU)

allowing handheld devices to display captured still images and

video directly on a TV or LCD projector. It supports the following analog video

outputs: composite, S-video, and component video up to HD720p/1080i.

TrustZone

Aware

Interrupt

Controller

ARM/Control

The TrustZone Interrupt Controller (TZIC) collects interrupt requests from all

i.MX51 sources and routes them to the ARM core. Each interrupt can be

configured as a normal or a secure interrupt. Software Force Registers and

software Priority Masking are also supported.

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6

10

Freescale Semiconductor

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