IN16C1054 View Datasheet(PDF) - IK Semicon Co., Ltd
Part Name
Description
Manufacturer
IN16C1054 Datasheet PDF : 53 Pages
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IN16C1054
5.3 Pin Description
Table 2: Pin Description
Data Bus Interface
Name
Pin
TQFP80
A0
48
A1
47
A2
46
D0
7
D1
8
D2
9
D3
11
D4
12
D5
13
D6
14
D7
15
IOR#
70
IOW#
31
CS0#
28
CS1#
33
CS2#
68
CS3#
73
INT0/GINT
27
INT1
34
INT2
67
INT3
74
INTSEL
6
PLCC68
34
33
32
66
67
68
1
2
3
4
5
52
18
16
20
50
54
15
21
49
55
65
Type Description
I
Address Bus Lines [2:0]. These 3 address lines select one
I
of the internal registers in UART channel 0-3 during a data
I
bus transaction.
I/O
Data Bus Lines [7:0]. These pins are tri-state data bus for
I/O
data transfer to or from the controlling CPU.
I/O
I/O
I/O
I/O
I/O
I/O
I
Read Data (active low strobe). A valid low level on IOR# will
load the data of an internal register defined by address lines
A [2:0] onto the UART data bus for access by an external
CPU.
I
Write Data (active low strobe). A valid low level on IOW# will
transfer the data from external CPU to an internal register
that is defined by address lines A [2:0].
I
Chip Select 0, 1, 2, and 3 (active low). These pins enable
I
data transfers between the external CPU and the UART for
I
the respective channel.
I
O
Interrupt 0/Global Interrupt, Interrupt 1, 2, and 3. These pins
O
provide individual channel interrupts or global interrupt.
O
INT0-3 are enabled when MCR[3] is set to ‘1’ and AFR[4] is
O
cleared to ‘0’ (default state). But INT0 operates as GINT and
INT1-INT3 are disabled when AFR[4] is set to ‘1’.
INT0-3’s asserted state is active high, but GINT’s asserted
state is determined by AFR[5]. GINT’s asserted state is
active high when AFR[5] is set to ‘1’, and active low when
AFR[5] is cleared to ‘0’.
I
Interrupt Select. When INTSEL is left open or low state, the
tri-state interrupts available on INT0-3 are enabled by
MCR[3]. But, when INTSEL is in high state, INT0-3 are
always enabled.
Rev. 00
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