IN16C1054 View Datasheet(PDF) - IK Semicon Co., Ltd
Part Name
Description
Manufacturer
IN16C1054 Datasheet PDF : 53 Pages
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IN16C1054
Table 2: Pin Description…continued
Name
TXRDY0#/TXEN0
TXRDY1#/TXEN1
TXRDY2#/TXEN2
TXRDY3#/TXEN3
Pin
TQFP80
21
40
61
80
PLCC68
-
-
-
-
RXRDY0#/RXEN0 20
-
RXRDY1#/RXEN1 41
-
RXRDY2#/RXEN2 60
-
RXRDY3#/RXEN3 1
-
TXRDY#
55
39
RXRDY#
54
38
Modem and Serial I/O Interface
Name
Pin
TQFP80 PLCC68
TXD0
29
17
TXD1
32
19
TXD2
69
51
TXD3
72
53
RXD0
17
7
RXD1
44
29
RXD2
57
41
RXD3
4
63
Type
O
O
O
O
O
O
O
O
O
O
Type
O
O
O
O
I
I
I
I
Description
Transmitter Ready 0, 1, 2, and 3/Tx Enable 0, 1, 2, and 3.
These pins provide individual channel transmitter ready or
transmit enable.
TXRDY0-3# are enabled when ATR[1:0] is cleared to ‘00’
(default state). If ATR[1:0] are set to ‘11’, TXRDY0-3#
operate as TXEN0-3.
TXRDY0-3# (active low) are asserted by TX FIFO/THR
status for transmit channels 0-3. TXEN0-3’s asserted state
is determined by ATR[5:4]. If ATR[4] is cleared to ‘0’, the
state holds the same value as ATR[5]. If ATR[4] is set to ‘1’,
it is the auto-toggling state based on ATR[5].
If these pins are unused, leave them unconnected.
Receiver Ready 0, 1, 2, and 3/Rx Enable 0, 1, 2, and 3.
These pins provide individual channel receiver ready or
receive enable.
RXRDY0-3# are enabled when ATR[1:0] is cleared to ‘00’
(default state). If ATR[1:0] is set to ‘11’, RXRDY0-3# are
changed to RXEN0-3.
RXRDY0-3# (active low) are asserted by RX FIFO/RBR
status for receive channels 0-3. RXEN0-3’s asserted state is
determined by ATR[7:6]. If ATR[6] is cleared to ‘0’, the state
holds the same value as ATR[7]. If ATR[6] is set to ‘1’, it is
the auto-toggling state based on ATR[7].
If these pins are unused, leave them unconnected.
Transmitter Ready (active low). This is asserted by TX
FIFO/THR status for transmit channels 0-3.
Receiver Ready (active low). This is asserted by RX
FIFO/RHR status for receive channels 0-3.
Description
Transmit Data. These pins are individual transmit data
output. During the local loop-back mode, the TXD output pin
is disabled and TXD data is internally connected to the RXD
input.
Receive Data. These pins are individual receive data input.
During the local loop-back mode, the RXD input pin is
disabled and RXD data is internally connected to the TXD
output.
Rev. 00
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