INDEX61075MHZ View Datasheet(PDF) - Intel
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INDEX61075MHZ Datasheet PDF : 48 Pages
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PENTIUM® PROCESSOR (610\75)
• Virtual Mode Extensions
2.1. Pentium® Processor Family
Architecture
The application instruction set of the Pentium
processor family includes the complete Intel486
CPU family instruction set with extensions to
accommodate some of the additional functionality
of the Pentium processors. All application software
written for the Intel386 and Intel486 family
microprocessors will run on the Pentium processors
without modification. The on-chip memory
management unit (MMU) is completely compatible
with the Intel386 family and Intel486 family of
CPUs.
The Pentium processors implement several
enhancements to increase performance. The two
instruction pipelines and floating-point unit on
Pentium processors are capable of independent
operation. Each pipeline issues frequently used
instructions in a single clock. Together, the dual
pipes can issue two integer instructions in one
clock, or one floating point instruction (under certain
circumstances, two floating-point instructions) in
one clock.
Branch prediction is implemented in the Pentium
processors. To support this, Pentium processors
implement two prefetch buffers, one to prefetch
code in a linear fashion, and one that prefetches
code according to the BTB so the needed code is
almost always prefetched before it is needed for
execution.
The floating-point unit has been completely
redesigned over the Intel486 CPU. Faster
algorithms provide up to 10X speed-up for common
operations including add, multiply, and load.
Pentium processors include separate code and
data caches integrated on-chip to meet perform-
ance goals. Each cache is 8 Kbytes in size, with a
32-byte line size and is 2-way set associative. Each
cache has a dedicated Translation Lookaside Buffer
(TLB) to translate linear addresses to physical
addresses. The data cache is configurable to be
writeback or writethrough on a line-by-line basis
and follows the MESI protocol. The data cache tags
are triple ported to support two data transfers and
an inquire cycle in the same clock. The code cache
is an inherently write-protected cache. The code
cache tags are also triple ported to support
snooping and split line accesses. Individual pages
can be configured as cacheable or non-cacheable
by software or hardware. The caches can be
enabled or disabled by software or hardware.
The Pentium processors have increased the data
bus to 64 bits to improve the data transfer rate.
Burst read and burst writeback cycles are
supported by the Pentium processors. In addition,
bus cycle pipelining has been added to allow two
bus cycles to be in progress simultaneously. The
Pentium processors' Memory Management Unit
contains optional extensions to the architecture
which allow 2-Mbyte and 4-Mbyte page sizes.
The Pentium processors have added significant
data integrity and error detection capability. Data
parity checking is still supported on a byte-by-byte
basis. Address parity checking, and internal parity
checking features have been added along with a
new exception, the ma chine check exception.
As more and more functions are integrated on chip,
the complexity of board level testing is increased.
To address this, the Pentium processors have
increased test and debug capability. The Pentium
processors implement IEEE Boundary Scan
(Standard 1149.1). In addition, the Pentium
processors have specified 4 breakpoint pins that
correspond to each of the debug registers and
externally indicate a breakpoint match. Execution
tracing provides external indications when an
instruction has completed execution in either of the
two internal pipelines, or when a branch has been
taken.
System Management Mode (SMM) has been
implemented along with some extensions to the
SMM architecture. Enhancements to the virtual
8086 mode have been made to increase
performance by reducing the number of times it is
necessary to trap to a vir tual 8086 monitor.
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