INDEX61075MHZ View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

INDEX61075MHZ

PENTIUM® PROCESSOR at iCOMP® INDEX 61075 MHz

Intel 

PENTIUM® PROCESSOR (610\75)

The block diagram shows the two instruction

pipelines, the "u" pipe and the "v" pipe. The u-pipe

can execute all integer and floating point

instructions. The v-pipe can execute simple integer

instructions and the FXCH floating-point

instructions.

The separate caches are shown, the code cache

and data cache. The data cache has two ports, one

for each of the two pipes (the tags are triple ported

to allow simultaneous inquire cycles). The data

cache has a dedicated Translation Lookaside Buffer

(TLB) to translate linear addresses to the physical

addresses used by the data cache.

The code cache, branch target buffer and prefetch

buffers are responsible for getting raw instructions

into the execution units of the Pentium processor.

Instructions are fetched from the code cache or

from the external bus. Branch addresses are

remembered by the branch target buffer. The code

cache TLB translates linear addresses to physical

addresses used by the code cache.

The decode unit decodes the prefetched

instructions so the Pentium processor can execute

the instruction. The control ROM contains the

microcode which controls the sequence of

operations that must be performed to implement the

Pentium processor architecture. The control ROM

unit has direct control over both pipelines.

The Pentium processors contain a pipelined

floating-point unit that provides a significant

floating-point performance advantage over previous

generations of processors.

The architectural features introduced in this section

are more fully described in the Pentium® Processor

Family Developer’s Manual .

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