INDR166B View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

INDR166B

Long Distance Digital Display Link Transmitter & Receiver

Unspecified 

Preliminary Data Sheet

INDT/R166B

INDT/R331B

The transmitter’s pixel interface accepts pixel data with a pixel clock frequency of 24 – 161 MHz (full pixel mode). For the

Tx side in single-ended mode, PX_CLK+ is the clock input and PX_CLK– has to be tied to GND. A differential pixel clcok

mode on the Rx side is not available. All pixel data and pixel clock inputs of the transmitter can be selected through the

VREF-pin to either work with conventional graphic controllers with 3.3 V output voltage swing or to work with latest

controllers with low voltage swing (1.0 – 2.0 V, see Figure 3.3: VREF Reference Circuitry). The pixel data and pixel

clock outputs of the receiver provide a 3.3 V CMOS compliant output.

1.2.2 Pixel Interface Modes

The pixel interface is configurable to accommodate all the various graphic interface standards in the market. The width of

the pixel interface is a function of the selected operating mode.

• In full-pixel mode the bit width of the pixel interface can be set to support an 18- or 24-bit wide parallel video interface.

1 pixel per sampling edge is transmitted.

• In double-pixel mode the bit width of the pixel interface can be set to support a 36- or 48-bit wide parallel video

interface. 2 pixels per sampling edge are transmitted.

1.2.3 Pixel Clock Sampling Modes

The pixel interface can be set to support data sampling at the rising, falling or at both edges of the pixel clock,

depending on the selected mode.

Table 1.4 and , Figure 1.4, Figure 1.5 summarize the various options for configuring the pixel interface.

Pixel Mode

18-bit

(Full Pixel)

24-bit

(Full Pixel)

36-bit

(Double

Pixel)

48-bit

(Double

Pixel)

Clock

Edge

rising

falling

both

rising

falling

both

rising

PX_CLK+

↑

↓

↑↓

↑

↓

↑↓

↑

falling

↓

rising

↑

falling

↓

PX_CLK-

–

–

–

–

–

–

–

–

–

–

Description

18 bits of pixel(n) sampled at rising edge of PX_CLK+

18 bits of pixel(n) sampled at falling edge of PX_CLK+

18 bits of pixel(n) sampled at both edges of PX_CLK+

24 bits of pixel(n) sampled at rising edge of PX_CLK+

24 bits of pixel(n) sampled at falling edge of PX_CLK+

24 bits of pixel(n) sampled at both edges of PX_CLK+

18 bits of pixel(n) and

18 bits of pixel(n+1) sampled at rising edge of PX_CLK+

18 bits of pixel(n) and

18 bits of pixel(n+1) sampled at falling edge of PX_CLK+

24 bits of pixel(n) and

24 bits of pixel(n+1) sampled at rising edge of PX_CLK+

24 bits of pixel(n) and

24 bits of pixel(n+1) sampled at falling edge of PX_CLK+

Table 1.4: Overview – Pixel Interface Configurations

Date: 2005-03-14 Revision: 0.1

Page 5 of 40

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