LE28F4001M View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LE28F4001M Datasheet PDF : 14 Pages
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LE28F4001M, T, R-15/20
7. Read ID operation
The read ID (identifier) operation consists of a single command, 90H. A read operation from address 0000H will
then return the manufacturer code (BFH) and a read operation from address 0001H will return the device code (04H).
This operation is terminated by writing any other valid command to the command register.
Protecting Data from Unintentional Writes
To protect the accumulated stored data that the user intends to be nonvolatile, the LE28F4001 Series products provide
both hardware and software functions to prevent unintentional writes when power is applied or cut off.
1. Hardware data protection
The LE28F4001 Series products incorporate a hardware data function that prevents unintentional writes.
• Write inhibit mode: Write operations are disabled if either OE is at the low logic level, CE is at the high logic
level, or WE is at the high logic level.
• Noise and glitch protection: WE pulses shorter than 15 ns will not execute a write operation.
• The LE28F4001 Series products were designed to hold unintentional writes to a minimum by setting the device to
read mode as the default when power is first applied.
2. Software data protection
As mentioned earlier, the LE28F4001 Series is designed to provide even more protection from unintentional writes
in software. To avoid unintentional erasure or programming of sector or device cells, when the application system
attempts to execute a sector erase or programming operation it must execute that operation as a two-stage sequence
consisting of first of a setup command and then an execute command.
As a default, the LE28F4001 Series products go to the write protected state after power is applied. The device goes to
the unprotected state after reads to seven specific addresses are executed consecutively. Those addresses are 1823H,
1820H, 1822H, 0418H, 041BH, 0419H, and 041AH. The address is latched on the rise of either OE or CE,
whichever is earlier. Similarly, the device can be set to the write protect state by reading from the following 7
addresses consecutively: 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, and 040AH. Figures 9 and 10 show the
software data protection waveforms for this 7-read-cycle sequence. The I/O pins can go to any state (high, low, or
high impedance).
Detection of Write Operation Completion
To acquire the maximum performance from the device, the application must detect the completion of the programming
cycle. The completion of the programming cycle can be detected by either Data polling or the toggle bit. This section
describes these two detection mechanisms.
Actually, the completion of a nonvolatile memory write operation is asynchronous with respect to the application
system. Therefore, it is possible that readout of either Data polling or toggle bit data could occur at the same time as the
completion of the write cycle. If this happens the application system might get an incorrect result. That is, valid data
could appear to contradict either DQ7 or DQ6. To prevent artificial rejections, if an incorrect result occurs, the software
routine must include a loop to read the accessed location another 2 times. If both these readout cycles acquire valid data
the device will have completed the write cycle. All other reject states are correct.
1. Data polling (DQ7)
The LE28F4001 Series products provide a Data polling function that detects the completion of the programming
cycle. During the program cycle, DQ7 reads out data that is the negation of the most recently loaded data. When the
programming cycle has completed, DQ7, along with DQ0 to DQ6, reads out the last loaded data. Figure 11 shows
the timing chart for this operation. For Data polling to function correctly, data must be erased before programming.
2. Toggle bit (DQ6)
The DQ6 toggle bit is another technique for detecting the end of the erase or programming cycle. During an erase or
programming operation the value of the DQ6 output alternates between 0 and 1, that is, the DQ6 output toggles
between 0 and 1. When the erase or programming cycle completes, the toggling stops and the device goes to a
normal read cycle. The toggle bit can be continuously monitored during an erase or programming cycle. Figure 12
shows the timing chart for toggle bit operation.
3. Continuous read
One more technique for detecting the end of an erase or programming cycle is to read the same address twice in a
row. If the same data is read twice in a row the erase or programming cycle has completed.
No. 5239-6/14
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