IS25LD256C View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

Manufacturer

IS25LD256C

256Kbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface

Integrated Silicon Solution 

IS25LD256C

DEVICE OPERATION (CONTINUED)

ERASE OPERATION

operation can be determined by reading the WIP bit in

the Status Register using a RDSR instruction. If the

The memory array of the IS25LD256C is organized

WIP bit is “1”, the erase operation is still in progress. If

into uniform 4 KByte sectors or 32KByte uniform blocks the WIP bit is “0”, the erase operation has been

(a block consists of eight adjacent sectors).

completed.

Before a byte can be reprogrammed, the sector or

BLOCK_ER COMMAND (BLOCK ERASE)

block that contains the byte must be erased (erasing OPERATION

sets bits to “1”). In order to erase the devices, there are

three erase instructions available: Sector Erase

A Block Erase (BLOCK_ER) instruction erases a 32

(SECTOR_ER), Block Erase (BLOCK_ER) and Chip KByte block of the IS25LD256C. Before the execution

Erase (CHIP_ER). A sector erase operation allows any of a BLOCK_ER instruction, the Write Enable Latch

individual sector to be erased without affecting the data (WEL) must be set via a Write Enable (WREN)

in other sectors. A block erase operation erases any instruction. The WEL is reset automatically after the

individual block. A chip erase operation erases the

completion of a block erase operation.

whole memory array of a device. A sector erase, block

erase or chip erase operation can be executed prior to The BLOCK_ER instruction code and three address

any programming operation.

bytes are input via SI. Erase operation will start

SECTOR_ER COMMAND (SECTOR ERASE)

immediately after the CE# is pulled high, otherwise the

BLOCK_ER instruction will not be executed. The

OPERATION

internal control logic automatically handles the erase

voltage and timing. Refer to Figure 17 for Block Erase

A SECTOR_ER instruction erases a 4 KByte sector Sequence.(address don’t care)

Before the execution of a SECTOR_ER instruction, the

Write Enable Latch (WEL) must be set via a Write

CHIP_ER COMMAND (CHIP ERASE) OPERATION

Enable (WREN) instruction. The WEL bit is reset

automatically after the completion of sector an erase

operation.

A Chip Erase (CHIP_ER) instruction erases the entire

memory array of a IS25LD256C. Before the execution

A SECTOR_ER instruction is entered, after CE# is

pulled low to select the device and stays low during the

entire instruction sequence The SECTOR_ER

instruction code, and three address bytes are input via

of CHIP_ER instruction, the Write Enable Latch (WEL)

must be set via a Write Enable (WREN) instruction.

The WEL is reset automatically after completion of a

chip erase operation.

SI. Erase operation will start immediately after CE# is

pulled high. The internal control logic automatically

handles the erase voltage and timing. Refer to Figure

16 for Sector Erase Sequence.

The CHIP_ER instruction code is input via the SI.

Erase operation will start immediately after CE# is

pulled high, otherwise the CHIP_ER instruction will not

be executed. The internal control logic automatically

handles the erase voltage and timing. Refer to Figure

During an erase operation, all instruction will be

18 for Chip Erase Sequence.

ignored except the Read Status Register (RDSR)

instruction. The progress or completion of the erase

Integrated Silicon Solution, Inc.- www.issi.com

21

Rev. A

09/11/2012

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