IS42S16400B1 View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS42S16400B1
Integrated Silicon Solution
IS42S16400B1 Datasheet PDF : 55 Pages
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IS42S16400B1
ISSI ®
PIN FUNCTIONS
Symbol
A0-A11
BA0, BA1
CAS
CKE
CLK
CS
DQ0 to
DQ15
LDQM,
UDQM
RAS
WE
VDDQ
VDD
GNDQ
GND
Pin No.
Type
Function (In Detail)
23 to 26
29 to 34
22, 35
Input Pin
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
20, 21
17
Input Pin
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
37
Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode. CKE is an asynchronous input.
38
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
19
Input Pin
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
2, 4, 5, 7, 8, 10,
11,13, 42, 44, 45,
47, 48, 50, 51, 53
DQ Pin
DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
15, 39
Input Pin
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. When LDQM or UDQM is HIGH, input data is masked and
cannot be written to the device.
18
Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.
16
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.
3, 9, 43, 49 Power Supply Pin VDDQ is the output buffer power supply.
1, 14, 27 Power Supply Pin VDD is the device internal power supply.
6, 12, 46, 52 Power Supply Pin GNDQ is the output buffer ground.
28, 41, 54 Power Supply Pin GND is the device internal ground.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. A
12/09/03
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