IS61C64B-10J(2002) View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

Manufacturer

IS61C64B-10J
(Rev.:2002)

8K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61C64B

AC WAVEFORMS

WRITE CYCLE NO. 1 (WE Controlled)(1,2)

tWC

ADDRESS

tSCE

tHA

CE

WE

DOUT

DIN

tAW

tPWE

tSA

tHZWE

DATA UNDEFINED

HIGH-Z

tLZWE

tSD

tHD

DATA-IN VALID

ISSI ®

WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)

tWC

ADDRESS

tSA

tSCE

tHA

CE

WE

DOUT

DIN

tAW

tPWE

tHZWE

DATA UNDEFINED

HIGH-Z

tLZWE

tSD

tHD

DATA-IN VALID

Notes:

1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the write.

2. I/O will assume the High-Z state if OE = VIH.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. D

07/01/02

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