IS61LV5128 View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

Manufacturer

IS61LV5128

512K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61LV5128

ISSI ®

WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle)

t WC

ADDRESS

OE

VALID ADDRESS

t HA

CE LOW

WE

DOUT

t SA

DATA UNDEFINED

t AW

t PWE1

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DIN

DATAIN VALID

CE_WR2.eps

Notes:

1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of

the signal that terminates the Write.

2. I/O will assume the High-Z state if OE • VIH.

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

t WC

ADDRESS

VALID ADDRESS

t HA

OE LOW

CE LOW

WE

DOUT

t SA

DATA UNDEFINED

DIN

t AW

t PWE2

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

CE_WR3.eps

8

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/16/01

Share Link: