ISL1220 View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
ISL1220 Datasheet PDF : 20 Pages
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ISL1220
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 5) MAX UNITS NOTES
VIH SDA and SCL Input Buffer HIGH
Voltage
Hysteresis SDA and SCL Input Buffer
Hysteresis
VOL SDA Output Buffer LOW Voltage,
Sinking 3mA
0.7 x
VDD
0.05 x
VDD
0
VDD +
V
0.3
V
0.4
V
Cpin
fSCL
tIN
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
TA = 25°C, f = 1MHz, VDD = 5V, VIN = 0V,
VOUT = 0V
Any pulse narrower than the max spec is
suppressed.
10
pF
400
kHz
50
ns
tAA
tBUF
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free before
the Start of a New Transmission
SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window.
SDA crossing 70% of VDD during a STOP
condition, to SDA crossing 70% of VDD
during the following START condition.
1300
900
ns
ns
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VDD crossing.
Measured at the 70% of VDD crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD.
From SDA falling edge crossing 30% of VDD
to SCL falling edge crossing 70% of VDD.
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
From SCL falling edge crossing 30% of VDD
to SDA entering the 30% to 70% of VDD
window.
1300
600
600
600
100
0
ns
ns
ns
ns
ns
900
ns
tSU:STO STOP Condition Setup Time
From SCL rising edge crossing 70% of VDD, 600
ns
to SDA rising edge crossing 30% of VDD.
tHD:STO STOP condItion Hold Time
From SDA rising edge to SCL falling edge. 600
ns
Both crossing 70% of VDD.
tDH Output Data Hold Time
From SCL falling edge crossing 30% of VDD,
0
ns
until SDA enters the 30% to 70% of VDD
window.
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1 x Cb
300
ns
6
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1 x Cb
300
ns
6
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
6
Rpu SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF.
1
Off-chip
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
kΩ
6
NOTES:
2. IRQ and FOUT Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
7. A write to register 08h should only be done if VDD > VBAT, otherwise the device will be unable to communicate using I2C.
4
FN6315.0
June 22, 2006
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