Philips Semiconductors
Triple RGB 6-bit video analog-to-digital
interface
Product specification
TDA8707
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
INPUT ISOLATION
αct
crosstalk between INR, ING and INB
−
−
−40 dB
Outputs (R0 to R5: pins 38 and 40 to 44; G0 to G5: pins 3 to 8; B0 to B5: pins 14 to 16 and 18 to 20)
VOL
LOW level output voltage
VOH
HIGH level output voltage
0
−
4.0
−
0.5 V
VDDD V
Switching characteristics
CLOCK INPUT CLK (see Fig.3)
fclk(max)
tCPH
tCPL
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
Analog signal processing (50% clock duty cycle) fclk = 35 MHz
35
−
10
−
12
−
−
MHz
−
ns
−
ns
LINEARITY
INL
DNL
integral non-linearity
differential non-linearity
ramp input; Tamb = 25 °C −
ramp input; Tamb = 25 °C −
BANDWIDTH (see Fig.5 and note 7)
B
−3 dB analog bandwidth
−
tSTLH
analog input settling time LOW-to-HIGH full scale square wave
−
tSTHL
analog input settling time HIGH-to-LOW full scale square wave
−
HARMONICS; note 6
f1
fundamental harmonic
−
fall
harmonics, all components
−
EFFECTIVE BITS
EB
effective bits
fi = 4.43 MHz
−
DIFFERENTIAL GAIN; note 5
Gdiff
differential gain
PAL modulated ramp
−
DIFFERENTIAL PHASE; note 5
ϕdiff
differential phase
PAL modulated ramp
−
Timing (see Figs 3 and 4)
tdS
sampling delay time
−
th
output hold time
6
td
output delay time
note 8
−
tr
clock rise time
3
tf
clock fall time
3
tCLP
active clamping duration
3
±0.35 ±0.6 LSB
±0.35 ±0.6 LSB
9
−
MHz
13
16
ns
11
14
ns
−
0
dB
−37 −
dB
5.3
−
bits
3
−
%
2
−
deg
3
−
ns
−
−
ns
−
16
ns
5
−
ns
5
−
ns
4
−
µs
1996 Feb 01
7