TDA8707 View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
TDA8707 Datasheet PDF : 16 Pages
| |||
Philips Semiconductors
Triple RGB 6-bit video analog-to-digital
interface
Product specification
TDA8707
Notes to the characteristics
1. VDDA and VDDD should be supplied from the same power supply and decoupled separately.
2. The analog supply current is directly proportional to the series resistance between VDDA and CLREF.
3. CREFH and CREFL are connected respectively to the top and bottom reference ladders of the 3 analog-to-digital
converters.
4. VI(p-p) = (VREFL − VREFH)/buffer gain factor. See Table for gain factor selection. When clamping at code 0 is used,
active video signal amplitude VACT should be: VACT = -(-b--V-u---fR--f-e-E---rF---Hg----a-–--i-n-V----f-R-a--E-c--F-t--o-L--r)--
5. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
6. VI(p-p) = ∆REF with fi = 4.43 MHz.
7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
8. Output data acquisition: output data is available after the maximum delay time of td.
Table 1 Typical output coding (VREFH = 2 V; VREFL = 0.5 V referenced to VSSA, SLT = logic 0; buffer ratio = 1.5;
Tamb = 25°C)
STEP
VI(p-p)
BINARY OUTPUT BITS
D5
D4
D3
D2
D1
D0
−
<0.333 = V-----1R---.E--5--F---L-
0
0
0
0
0
0
0
0.349
0
0
0
0
0
0
1
0.364
0
0
0
0
0
1
.
.
.
.
.
.
.
62
1.317
1
1
1
1
1
0
63
1.333
1
1
1
1
1
1
−
>1.333 = V-----R1---E.--5--F---H-
1
1
1
1
1
1
Table 2 Mode selection
SLT
BUFFER RATIO
0
1.5
1
2.0
TYPICAL VI(p-p) FULL SCALE
V-----R---E----F---H-1---–-.-5---V----R----E---F---L-
V-----R---E----F---H-2---–-.-0---V----R----E---F---L-
1996 Feb 01
8
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