ISPGDX160V-9Q208I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

ISPGDX160V-9Q208I

In-System Programmable 3.3V Generic Digital Crosspoint

Lattice Semiconductor 

Specifications ispGDX160V/VA

Figure 3. Adjacent I/O Cells vs. Direct Input Path for Special Features

ispGDX160V/VA, I/O D23

Slew Rate Control

ispGDX160V/VA I/O Cell

I/O Group A

All output buffers contain a programmable slew rate

D21 MUX Out

I/O Group B

D22 MUX Out

S I/O Group C

D24 MUX Out

E I/O Group D

D25 MUX Out

4x4

Crossbar

Switch

S1 S0

.m0

.m1

D23

.m2

.m3

IC It can be seen from Figure 3 that if the D21 adjacent I/O

cell is used, the I/O group “A” input is no longer available

D as a direct MUX input.

V The ispGDXV/VA can implement MUXes up to 16 bits

E wide in a single level of logic, but care must be taken

when combining adjacent I/O cell outputs with direct

E MUX inputs. Any particular combination of adjacent I/O

U cells as MUX inputs will dictate what I/O groups (A, B, C

or D) can be routed to the remaining inputs. By properly

D choosing the adjacent I/O cells, all of the MUX inputs can

IN be utilized.

control that provides software-selectable slew rate op-

tions.

Open Drain Control

All output buffers provide a programmable Open-Drain

option which allows the user to drive system level reset,

interrupt and enable/disable lines directly without the

need for an off-chip Open-Drain or Open-Collector buffer.

Wire-OR logic functions can be performed at the printed

circuit board level.

Pull-up Resistor

All pins have a programmable active pull-up. A typical

resistor value for the pull-up ranges from 50kΩ to 80kΩ.

Output Latch (Bus Hold)

All pins have a programmable circuit that weakly holds

the previously driven state when all drivers connected to

the pin (including the pin's output driver as well as any

other devices connected to the pin by external bus) are

tristated.

T Table 2. Adjacent I/O Cells (Mapping of

T ispGDX160V/VA)

C Data A/ Data B/ Data C/ Data D/

N MUXOUT MUXOUT MUXOUT MUXOUT

B20

B22

B21

B19

B18

E B21

B23

B22

B20

B19

O B22

B24

B23

B21

B20

L Reflected B23

B25

B24

B22

B21

I/O Cells D16

D18

D17

D15

D14

E C D17

D19

D18

D16

D15

D18

D20

D19

D17

D16

S IS D19

D21

D20

D18

D17

D20

D18

D19

D21

D22

D21

D19

D20

D22

D23

D D22

D20

D21

D23

D24

ispGDX160VA New Features

Unique to the ispGDX160VA are user-programmable

I/Os supporting either 3.3V or 2.5V output voltage level

options. The ispGDX160VA uses a VCCIO pin to provide

the 2.5V reference voltage when used. The ispGDX160VA

VCCIO pin occupies the same location as VCC on the

ispGDX160V, allowing drop-in replacement. The

ispGDX160VA offers improved performance by reducing

fanout delays and has PCI compatible drive capability.

Only the ispGDX160VA is available in the fastest (3.5ns)

Commercial speed grade and in -5,-7, and -9ns Industrial

grades in all packages.

The ispGDX160VA has a device ID different from the

ispGDX160V requiring that the latest Lattice download

software be used for programming and verification. Al-

Normal D23

I/O Cells

B16

B17

B18

D21 D22

B14 B15

B15 B16

B16 B17

D24 D25

B17 B18

B18 B19

B19 B20

though the ispGDX160VA and ispGDX160V are

functionally equivalent, they are not 100% JEDEC com-

patible. All design files must be recompiled targeting the

ispGDX160VA.

B19

B17

B18

B20

B21

5

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