M48T251VPM View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M48T251VPM

5.0 or 3.3V, 4096K TIMEKEEPER® SRAM with PHANTOM

STMicroelectronics 

M48T251Y, M48T251V

Data Retention Mode

Data can be read or written only when VCC is

greater than VPFD. When VCC is below VPFD (the

point at which write protection occurs), the clock

registers and the SRAM are blocked from any ac-

cess. When VCC falls below the Battery Switch

Over threshold (VSO), the device is switched from

VCC to battery backup (VBAT). RTC operation and

SRAM data are maintained via battery backup un-

til power is stable. All control, data, and address

signals must be powered down when VCC is pow-

ered down.

The lithium power source is designed to provide

power for RTC activity as well as RTC and RAM

data retention when VCC is absent or unstable.

The capability of this source is sufficient to power

the device continuously for the life of the equip-

ment into which it has been installed. For specifi-

cation purposes, life expectancy is ten (10) years

at 25°C with the internal oscillator running without

VCC. Each unit is shipped with its energy source

disconnected, guaranteeing full energy capacity.

When VCC is first applied at a level greater than

VPFD, the energy source is enabled for battery

backup operation. The actual life expectancy will

be much longer if no battery energy is used (e.g.,

when VCC is present).

PHANTOM CLOCK OPERATION

Communication with the Phantom Clock is estab-

lished by pattern recognition of a serial bit-stream

of 64 bits which must be matched by executing 64

consecutive WRITE cycles containing the proper

data on DQ0.

All accesses which occur prior to recognition of the

64-bit pattern are directed to memory.

After recognition is established, the next 64 READ

or WRITE cycles either extract or update data in

the clock while disabling the memory.

Data transfer to and from the timekeeping function

is accomplished with a serial bit-stream under con-

trol of Chip Enable (CE), Output Enable (OE), and

WRITE Enable (WE). Initially, a READ cycle using

the CE and OE control of the clock starts the pat-

tern recognition sequence by moving the pointer to

the first bit of the 64-bit comparison register (see

Figure 8., page 12).

Next, 64 consecutive WRITE cycles are executed

using the CE and WE control of the device. These

64 WRITE cycles are used only to gain access to

the clock. Therefore, any address to the memory

is acceptable. However, the WRITE cycles gener-

ated to gain access to the Phantom Clock are also

writing data to a location in the mated RAM. The

preferred way to manage this requirement is to set

aside just one address location in RAM as a Phan-

tom Clock scratch pad.

When the first WRITE cycle is executed, it is com-

pared to Bit 1 of the 64-bit comparison register. If

a match is found, the pointer increments to the

next location of the comparison register and

awaits the next WRITE cycle.

If a match is not found, the pointer does not ad-

vance and all subsequent WRITE cycles are ig-

nored. If a READ cycle occurs at any time during

pattern recognition, the present sequence is abort-

ed and the comparison register pointer is reset.

Pattern recognition continues for a total of 64

WRITE cycles as described above until all of the

bits in the comparison register have been

matched. With a correct match for 64-bits, the

Phantom Clock is enabled and data transfer to or

from the timekeeping registers can proceed. The

next 64 cycles will cause the Phantom Clock to ei-

ther receive or transmit data on DQ0, depending

on the level of the OE pin or the WE pin. Cycles to

other locations outside the memory block can be

interleaved with CE cycles without interrupting the

pattern recognition sequence or data transfer se-

quence to the Phantom Clock.

11/24

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