M48T251V-70PM1 View Datasheet(PDF) - STMicroelectronics
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Description
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M48T251V-70PM1 Datasheet PDF : 24 Pages
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M48T251Y, M48T251V
OPERATION MODES
Table 2. Operating Modes
Mode
VCC
CE
Deselect
VIH
WRITE
4.5V to 5.5V
VIL
or
READ
3.0V to 3.6V
VIL
READ
VIL
Deselect
VSO to VPFD (min)(1)
X
Deselect
≤ VSO(1)
X
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage
1. See Table 12., page 20 for details.
READ
A READ cycle executes whenever WRITE Enable
(WE) is high and Chip Enable (CE) is low (see Fig-
ure 5.). The distinct address defined by the 19 ad-
dress inputs (A0-A18) specifies which of the 512K
bytes of data is to be accessed. Valid data will be
accessed by the eight data output drivers within
the specified Access Time (tACC) after the last ad-
Figure 5. Memory READ Cycle
OE
WE
DQ7-DQ0
Power
X
X
High-Z
Standby
X
VIL
DIN
Active
VIL
VIH
DOUT
VIH
VIH
High-Z
Active
Active
X
X
High-Z
CMOS Standby
X
X
High-Z
Battery Back-Up
dress input signal is stable, the CE and OE access
times, and their respective parameters are satis-
fied. When CE tACC and OE tACC are not satisfied,
then data access times must be measured from
the more recent CE and OE signals, with the limit-
ing parameter being tCO (for CE) or tOE (for OE) in-
stead of address access.
ADDRESSES
CE
OE
DQ0 - DQ7
Note: WE is high for a READ cycle.
tRC
tACC
tCO
tOE
tCOE
tCOE
tOH
tOD
tODO
DATA OUTPUT
VALID
AI04230
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