K4S161622H-TC55 View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
K4S161622H-TC55 Datasheet PDF : 11 Pages
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SDRAM 16Mb H-die(x16)
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig. 2
3.3V
Output
870Ω
1200Ω
30pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
CMOS SDRAM
Z0=50Ω
Unit
V
V
ns
V
Vtt=1.4V
50Ω
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
CLK cycle time
CAS Latency=3
tCC
CAS Latency=2
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to new col.address delay
tCDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Mode Register Set cycle time
tMRS(min)
Number of valid out-
put data
CAS Latency=3
CAS Latency=2
55
Min Max
5.5
1000
10
11
-
16.5 -
16.5 -
38.5 -
-
100
55
-
2
60
70
Min Max Min Max
6
7
1000
1000
10
10
12
-
14
-
18
-
20
-
18
-
20
-
42
-
49
-
-
100
-
100
60
-
69
-
1
1
1
1
2
2
1
80
Min Max
8
1000
10
16
-
20
-
20
-
48
-
-
100
70
-
Unit
ns
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
CLK
ea
Note
1
2,8
2
2
4
Rev. 1.5 August 2004
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