KS9287 View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

KS9287

DIGITAL SIGNAL PROCESSOR

Samsung 

DIGITAL SIGNAL PROCESSOR

KS9287

PIN DESCRIPTION (Continued)

No. Pin Name I/O

Description

33

SBDT

O Subcode data serial output

34

VDD

- Digital VDD

35

MUTE

I Mute control input ("H": Mute ON)

36

MLT

I Latch Signal Input from MICOM

37

MDAT

I Serial data input from MICOM

38

MCK

I Serial data transfering clock input from MICOM

39

RD7

I/O SRAM data I/O port (MSB)

40

RD6

I/O SRAM data I/O port 6

41

RD5

I/O SRAM data I/O port 5

42

RD4

I/O SRAM data I/O port 4

43

RD3

I/O SRAM data I/O port 3

44

RD2

I/O SRAM data I/O port 2

45

RD1

I/O SRAM data I/O port 1

46

RD0

I/O SRAM data I/O port 0 (LSB)

47

FLAG1

I/O Monitoring output for ECC (RA0)

48

FLAG2

I/O Monitoring output for ECC (RA1)

49

FLAG3

I/O Monitoring output for ECC (RA2)

50

FLAG4

I/O Monitoring output for ECC (RA3)

51

FLAG5

I/O Monitoring output for ECC (RA4)

52

/PBCK

I/O VCO/2 clock output (4.3218 MHz) (RA5)

53

VSS

I/O Digital ground

54

FSDW

I/O Frame Sync protection Window (RA6)

55

ULKFS

I/O Frame sync protection status (RA7)

56

/JIT

I/O Display of either RAM overflow or underflow for ±4 frame jitter margin (RA8)

57

C4M

I/O 4.2336 MHz signal output (RA9)

58

C16M

I/O 16.9344 MHz signal output (RA10)

59

/WE

I/O Write enable signal for external SRAM

60

/CS

I/O Chip select signal for external SRAM

61

XTALSEL

I Mode Selection1 (H: 33.8688 MHz, L: 16.9344 MHz)

62

DPLL

I Mode Selection2 (H: APLL, L: DPLL)

63

CDROM

I Mode Selection3 (H: CD-ROM, L: CDP)

64

SRAM

I Mode selection4 (H: External SRAM, L: Internal SRAM)

6

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